Eric Bogatin’s Blog: What I Learned This Month

There is an old joke told by Henny Youngman (1906 –1998) that goes something like this,

A man goes to a doctor and says to him, “Doctor, it hurts when I raise my arm, what should I do?” the Doctor says, “Don’t raise your arm.”

Surprisingly, this is an excellent strategy to follow to design signal integrity problems out of your next product. The details of this strategy are a core part of the Essential Principles of SI (EPSI) class I teach. Here’s a brief snapshot and a glimpse at how you apply the “Youngman Principle”.

The first step in designing SI problems out of your product is to identify the signal integrity problems to avoid. The next step is to identify the root cause of the problem. If you know the root cause, it often screams out at you (in pain) the way to avoid the problem.

For example, a common problem to avoid is reflection noise. The root cause is, that when the instantaneous impedance the signal sees changes, a reflection is created. Reflections that rattle around create ringing. How do you eliminate this problem? If it hurts when the instantaneous impedance changes, don’t change the instantaneous impedance. This means use controlled impedance interconnects, manage the reflections at the ends of lines with a termination strategy and use a routing topology that is linear.

Ground bounce is the most difficult problem to eliminate because it can reach very large voltages, can be long range, is poorly understood by most engineers, and involves the return path, which is often hard to trace out. The problem is voltage noise injected on signal lines when nearby signal lines switch.

The root cause of ground bounce is two fold. First, the return path of a signal needs to be screwed up from the usual wide return path. Second, the return path of one conductor needs to share this return path of another conductor.

If it hurts when the return path is not in a wide plane and when the return paths are shared, don’t screw up the return path and don’t share return paths.

If you can figure out the root cause of a problem, it screams out at you, when you do this, (raise your arm), the problem arises. The solution is, as Henny Youngman points out, “don’t raise your arm!”

To learn about the root cause of some of the common signal integrity problems, check out the articles I have on my web site.

One of the most common questions I get asked in my Essential Principles class is why does everyone use 50 Ohms? what’s so special about 50 Ohms? The answer, like so many standards we use today, has its origin in a practical application at the time which may not apply today.

50 Ohms had its origin in the early days when transmission lines were first getting popular, with radio and radar system. When the generation and transmission of an rf signal is not very efficient, every milliwatt of power is precious.  To minimize the losses in the cables from the rf generator to the transmitting antenna, you want to use the lowest loss cable you can.

In a coax cable, what is the impedance to use that gives the lowest loss per length?

The losses in a coax cable are dominated by the conductor loss, which depends on the series resistance of the inner conductor and outer conductors. Since above about 1 MHz, all the current is skin depth limited, it is the circumference of the conductors that influence the series resistance. The larger the circumference, the lower the series resistance.

But, the attenuation depends on the series resistance divided by the characteristic impedance. If the outer diameter of the cable is fixed- you use the largest diameter you can- then the only parameter to adjust is the diameter of the inner conductor.

If you increase the inner diameter, the series resistance decreases, which is good, but the characteristic impedance decreases, which is bad. As you sweep the inner diameter from really small to close to the outer conductor diameter, and ask, how does the attenuation vary, there is a minimum value. What is the impedance of the cable when the attenuation is a minimum?

It’s very easy to “put in  the numbers”  using the simple approximations for attenuation and the impedance of a coax cable found in my book. When you plot the attenuation vs characteristic impedance of a coax cable, as shown to the left, you find there is an impedance that gives the lowest attenuation. When the dielectric constant is 2, this is just about 50 ohms. Even if the dielectric constant is higher, closer to 4, it is still close to 50 ohms.

Of course, few high speed digital systems are limited by attenuation in coax cables. But  the same principles can be used to find the optimum impedance for lowest loss, or lowest power dissipation, or lowest cross talk, or thinnest dielectric layers.  Depending on which of these features is the most important for your design, the optimum impedance will range from around 40 ohms to 80 ohms single ended, or 80 to 150 ohms differential impedance.

The details on performing these trade offs is covered in our High Speed Design Principles class. Hope to see you there sometime.

To paraphrase Heraclitius of Ephesus (535 BC - 475 BC), “The only constant is change.” This mantra has driven the electronics world since the inception of the tube in the early 1910’s. The latest advance in 3D chips may be a glimpse into the next wave for electronics.

We usually hear about the active part of the system as what drives the advance of electronics, but the interconnects have played just as vital a role in increasing functional density in the last nearly 100 years. It can be argued that the interconnects have even lead advances in the active components.

The vacuum tubes used discrete wiring. They evolved into the transistor. The printed circuit board was created to increase the functional density of discrete transistors. The integrated circuit miniaturized the circuit board interconnects and enabled orders of magnitude increases in functional density and launched the treadmill of Moore’s Law.

In this phase, we evolved an alphabet soup of individual package styles: DIP, PQFP, PGA, LGA, BGA, CSP. Circuit board technology evolved to micro vias and HDI to keep up with the interconnect density demands of the CSP introduced in the early 1990s. I’ve written three books and numerous articles on these technologies.

Packaging technology took the functional density lead with the introduction of the multi-chip package. One packaged component had the functional density of a chip two or three silicon-generations away. IC technology followed in packaging’s footsteps with the System on a Chip (SoC) and multi-core processors. And multi-chip modules changed its name to System in Package (SiP) to sound cooler.

However wonderful the advances of SoC and SiP are to advance functional density, they will always live in a planar world,  limited to one or at most, two surfaces. Packaging technology allowed close to 100% packaging efficiency, but it could never exceed what the silicon was capable.

Packaging technology took the lead in breaking the bounds of the 2D world, with stacked chips. Starting with flash and SRAMs for cell phones, there are no fundamental limits to stacked die modules. The packaging efficiency exceeds 400% in some applications.

While silicon technology has made small forays into the 3D world, with laminated silicon layers and  thru-silicon-vias, such as this IBM illustration shown to the left, none of them have shown legs…until this recent announcement of 3D integrated circuits.

The first 3D chip is running at 1.4 GHz at the University of Rochester. This is not a collection of stacked layers, it is an integrated design specifically optimized for 3D with all key processes functioning vertically through multiple layers of processors.

“I call it a cube now, because it’s not just a chip anymore,” says Eby Friedman, Distinguished Professor of Electrical and Computer Engineering at Rochester and co-creator of the processor. “This is the way computing is going to have to be done in the future. When the chips are flush against each other, they can do things you could never do with a regular 2D chip.”

Of course there are challenges ahead, but that’s exactly what was said at the beginning of the IC era. Functional density in 2D will always operate at the most cost effective point of the integration vs yield curve.  This defines the largest chip possible. Packaging technology will always give the silicon the next boost in functional density. But now, there is a glimpse of how silicon technology might be able to jump to the next level of functional density by growing in the third dimension.

“Are we going to hit a point where we can’t scale integrated circuits any smaller? Horizontally, yes,” says Friedman. “But we’re going to start scaling vertically, and that will never end. At least not in my lifetime. Talk to my grandchildren about that.”

Want to read more about the dance between packaging and silicon technology, check out the columns and feature articles on my web site, www.beTheSignal.com.

I noticed that Agilent is offering a slew of live signal integrity events in the next month.

From Sept 16 - Oct 17, there is the  “High-Speed Digital Seminar - Tackling High-Speed Serial Designs“. This is a series of presentations on SI issues, like DDR, PCIe, PLLs, Gbps FPGAs and VNA and TDR techniques. If you don’t know what the TLAs and FLAs*** are, this seminar is probably for you.  This is like a what’s what in SI today. Though it is moving around to six different locations, I am disappointed that I will not be around to catch any of them! I hope Agilent makes the talks available on a CD.

On Sept 22, there is a 1-day event, Interconnect Analysis and Modeling Workshop. This looks like it covers the use of TDR, VNA, PLTS and ADS for SI applications. Lots of instrument and simulation demos for sure.

On Oct 21-24 there is a 3-day hands on workshop, Designing for Signal Integrity with ADS. This is a soups to nuts class on getting started with ADS for SI applications. For those of you who have tried to get up to speed on ADS on your own, it is a little confusing. All you need is about 30 minutes with someone showing you the style of ADS simulations and you will see it is simple and straight forward.  This class can give you a jump start to accelerate you up the learning curve of being productive with ADS.

***ok, TLA is Three Letter Acronym and FLA is Four Letter Acronym

Pencils down! The results of the latest pop quiz are in. The question posted on www.beTheSignal.com a few weeks ago was “A data stream has a 10-90 rise time of about 300 psec. What is the approximate bandwidth of the signal?”

There were 303 answers submitted. Our web site assures that a person can submit only 1 answer.  70% of you got it correct.

The bandwidth of a signal is the highest sine wave frequency component in eh signal. As a pretty good approximation, the bandwidth of a signal is about 0.35/RT, where RT is the 10-90 rise time.

In this example, the rise time is 0.3 nsec, so the bandwidth is about 0.35/0.3 = 1 GHz. Of course, this assumes a linear or gaussian edge shape. If it is grossly distorted, or has a long tail, such as with a lossy line, the 10-90 rise time can be long, and this approximation would be an under estimate.

The use of the term bandwidth is always only a rough approximation. If it is important whether the bandwidth is 1.1 GHz or 1.3 GHz, don’t use the bandwidth, use the entire spectrum. Want to know more about rise time and bandwidth, see chapter 2 in my book, or attend the EPSI class.

For you puzzle geeks, a new pop quiz has been posted! The answer will appear in this blog in a few weeks.

I was not able to attend the EMC 2008 Symposium in Detroit last month, but I did take a look at some of the papers.  One in particular caught my eye: “Signal Integrity Analysis of a 26 Layer Board with Emphasis on the Effect of Non-Functional Pads”, by Anthoni Ciccomaanccini Scogna, with CST.

Do vias look inductive or capacitive? What is the most common answer to all signal integrity questions? “It depends”. Anthoni does a nice job of showing that by adjusting the non-functional pads (NFPs) in vias with adjacent return vias, you can switch a long via from looking capacitive to looking inductive. There is a “Goldilocks” solution somehwere in between.

It is pretty well know that non-functional pads increase the capacitance of a via and especially for long vias, makes their impedance a little low. This degrades their bandwidth. Removing non-functional pads will usually bring the impedance up, closer to 100 ohms differential.

Anthoni use a 0.32 inch thick backplane as a test vehicle to explore this question of whether the NFPs should be removed or not. He took a cookie cutter section from the backplane board, containing  two pairs of differential vias with associated, adjacent return vias. The cross section is shown to the left, for just one of the differential pairs. The colors also show the current density for a common signal.

He brought the 3D physical model into CST, a 3D full wave solver. He then used his tool to calculate the differential return and insertion losses, in both the frequency domain and time domain, for a signal going from the top surface, through a very long via to a layer near the bottom of the board.

With a way of predicting performance, he was able to go into the design and remove all the non-functional pads.  The best comparison is in looking at the simulated TDR response through the differential pair, for the case with the NFPs and when they are removed.

He found that with the NFPs, the response looked very capacitive, while after the NFPs were removed, the via path looked a little inductive.  In the TDR plots to the left, the blue trace is with the NFPs, while the pink trace is with the NFPs removed.

The answer he gave to the question of whether to remove the NFPs was the most common answer to all SI questions: It depends.

In general, removing the NFPs makes the via inductive.  While it is closer to 100 ohms differential than with the NFPs, it has room for improvement. He concludes that if you really want to optimize your via design, you probably want to use a 3D field solver to find the right combination of clearance hole and NFP size to bring the via closer to 100 Ohms.

I would add that the residual stubs present in all vias tends to move the vias toward the capacitive side and even with all the  NFPs removed, most long vias will look capacitive. If you are not going to run your own 3D simulation, I think, as a good design guideline, remove your NFPs.

If you are interested in via design, this is one of the topics covered in our High Speed Design Principles Class (HSDP).  Check the web site for the scehdule.

I was revising my lecture on ground bounce in the Essential Principles of SI class and found a very simple rule of thumb for describing the total inductance of the return path of a conductor. Ground bounce is all about the voltage created across the return path conductor when the return current of a signal line passes through it.

Of course, if there is no other conductor sharing this same return path, then the ground bounce noise generated may be a “who cares”. However, if another signal path also uses the same conductor for its return path- shared return paths- then the ground bounce noise created by the first signal switching will be seen as noise by the innocent victim line.

The amount of ground bounce generated depends on the total inductance of the signal path and the dI/dt of the switching current. This can be on the order of 20 mA/nsec for a 1 nsec rise time signal, or even 60 mA/nsec, for a 300 psec rise time signal, such as found in DDR3 signals.

But what is a good estimate for the total inductance of the return path? Is it 0.1 nH, 1 nH, or even 10 nH? Of course, the most common answer to all signal integrity questions- and most others- is “it depends”. However, sometimes, an OK answer NOW! is better than a good answer late. If you want a rough estimate NOW!, a rule of thumb is the tool to use.

For other than a few simple geometries, inductance is really hard to calculate. The approximations available are pretty complicated. I used the built in 2D field solver, and integrated circuit simulator in Agilent’s ADS to calculate for me the total inductance for a simple geometry of two adjacent, rectangular signal lines, such as might be found in a leaded package. Each line has the same line width and there is some spacing between the two lines.

I then fixed the spacing and swept the line width. The total inductance per length of one of the lines is what is plotted in the figure. It has the features expected. As the width of the return path increases, its total inductance decreases. As the spacing between them decrease, the total inductance also decreases.

What is interesting is that for the case of the line width equal to the spacing, independent of the line width, the total inductance is pretty darn close to 10 nH/inch. This makes for a simple, easy to remember rule of thumb.

When the signal and return path conductors are of the same size and the spacing between them is on the order of their line width, the total inductance of the return path is 10 nH/inch.

If the lead lengthis 0.5 inches, this is 5 nH of total inductance. One DDR3 signal line switching through this will generate 5 nH x 60 mA/nsec = 300 mV of ground bounce. Let three signals switch throug the same common lead and you get almost 1 v of ground bounce. That’s a lot! and not so uncommon.

If you want to learn more about inductance, check out more of the content on our web site relating to inductance, cross talk, switching noise and ground bounce at www.beTheSignal.com.

I had an interesting conversation with Shankar Srinivasan, a research scientist at the Edison Welding Institute. He and his team have developed a clever way of enabling soldering with a variety of solders without flux.

The purpose of a flux is to chemically reduce the oxide layers present on all tin surfaces. Remove the oxides and the metals can wet and you get a metallurgical bond. The problem with fluxes is that they are full of corrosive chemicals. If you leave any flux residue on the surface there is the potential of corrosion which is a long term reliability problem.

What Shankar’s team has developed is an ultrasonic soldering tool that uses cavitation at the tip to disrupt and dislocate oxides at the surface of the metals being joined. The molten solder acts as the acoustic transfer medium for the ultrasonic energy. The cavitating micro bubbles burst on all surfaces, cleaning the surfaces and exposing wettable, oxide-free metal.

This technique can be applied to a variety of solders, lead free in particular, and a variety of metal surfaces. It may have immediate application in hand soldering, repair and rework and in some wave solder applications. Eliminating the use of flux means no cleaning operations are needed, which means no waste water, and that will contribute to a greener process.

Interested in more technology topics, check out the columns I’ve written that are posted on www.beTheSignal.com.

Surfing the web can be an infinite time sink and it can quickly lead to information overload syndrome. While there is a lot of stuff in cyberspace, not all of it is worth the time to open the page and close it. Periodically, I’ll share some of the sites I come across that I think are exceptionally useful for signal integrity engineers. I’ll try to keep these listed on my web site, beTheSignal.com, in the resources section. Here are a few sites I’ve visited recently I think are important.

Prentice Hall, my publisher, has created a series of books on signal integrity. These have been bundled into the Modern Semiconductor Design Series. There are now 34 titles in this series. At an average of 2 inches in thickness each, this is about five feet of signal integrity. If you are starting a library, or want to suggest some books for your company library as must haves, this is a great place to start.

A number of large semiconductor companies have an applications engineering center for their customers. Altera Corp offers a Signal Integrity Center with a bunch of app notes, webinars, columns, models, tools and case studies with design guidelines.

Agilent Technologies has a similar deal, providing a portal to all the SI applications on their extensive web site. Here you will find links to app notes, webinars, product technical reports and descriptions of tools and techniques to characterize passive interconnects and active signals.

Agilent sometimes suffers from multiple personality disorder. They excel in both the hardware side of the SI solution and the software side, with their ADS tool suite. Though they are still learning to play together, as an end user, we often have to deal with them as separate companies. For the SI portal to Agilent software product applications, again, an extensive collection of app notes, videos, and webinars, check out their web site.

While we are talking about Agilent, there is also the new SI blog that Colin Warwick, a product marketing manager with the software side of the company, has created. For a marketing guy, he is pretty sharp technically and always has an interesting tip to share.

Another blog I visit regularly is Rick Merritt’s, an editor for EE Times. As a journalist for EE Times, he has his finger on the pulse of what’s happening in our industry.

In addition, the other popular journalist with a blog who covers our field is Paul Rako, editor with EDN. He covers the whole analog field, not just signal integrity.

There are many, many more web sites with valuable info and I will mention some of them in future posts. Please send me your comments on your favorite sites and I will consider adding them to my blog and to the resources page of my web site.

As Kansas is not a hot bed of signal integrity, I have to travel to most of the classes I do. Last week, I taught  a class in Ft Collins, CO and decided to drive across the state. Everyone complains about how flat and boring Kansas is. However, on this trip, I passed some new scenery which I think will become much more common in Kansas and other states.

On the US Dept of Energy map of wind power in the US, it is clear why tornado alley, where I live, is also wind power alley. Kathleen Sebelius, the governor of Kansas, has called Kansas the Saudi Arabia of wind. The US Dept of Energy estimates that 20% of the US electricity demands can come from the wind in this corridor. As an example, one of the 3 Mega-watt turbines pictured above can generate the energy equivalent of 12,000 barrels of oil in 1 year.

This is part of the basis of the plan T.Boone Pickens revealed last week in Topeka, Kansas. You’ve seen his “I’ve got a plan” promo ads on TV. He decided to kick off his nation wide tour to describe the details of this plan with a first stop in the wind capital of the US, Topeka.  After recently seeing first hand the growth of wind farms in Kansas, Susan and I decided to attend his standing room only presentation.

He started out writing the number $700B on the board. This is the money the US spends on imported oil each year. We effectively burn this money, while our suppliers invest it. His plan to wean the US from foreign oil is to first replace the current electricity production from natural gas with wind power. Second, create an electrical power distribution grid to transmit this generated power throughout the US. The third part of his plan is to promote the use of natural gas powered cars.

While I completely agree with his vision of the problem and the use of wind and other renewable energy sources, and the installation of a transmission infrastructure, I disagree with him about the car power of the future. I think we should look to transition our society from the era of hydrocarbons to the era of renewable energy resources. As we say in technology development, I think investing in developing efficient electric cars has more head room than a similar investment in natural gas car.

New advances like MIT Chemist, Daniel Nocera’s, catalyst that cracks water into hydrogen and oxygen with solar energy could directly feed the needs of an electric vehicle fleet.

How’s all this tie into beTheSignal.com? If any of you have watched our online lectures, you’ve noticed our copyright page with the tornado theme. Given the role Kansas will play in the future, we are changing the tornado theme to a wind energy generation theme.

I’m working on a series of online lectures on power integrity, to be released in the next month. Sign up on the web site and you will be notified when they are released. Look for the windmills and think of renewable energy technologies.