Eric Bogatin's Blog: What I Learned This Month

Getting started in signal integrity? check out the pdf copy of Chapter 1 from Signal and Power Integrity- Simplified, available for free download on www.beTheSignal.com

Getting started with IBIS-AMI models? read on….

You cannot predict the performance of a high speed serial link without having an accurate model for the transmitters (TX), the channel, and the receivers (RX). These days, the channel model, ultimately represented by its S-parameters, is the easy part.

If you can describe a single differential channel in terms of the S-parameters from one end to the other, you can incorporate it into most simulators. This could be a touchstone file with an .s4p extension, for example, signifying a 4-port S-parameter data set.

Even better, if you can include the S-parameters for one or two adjacent channels, you can include the impact from uncorrelated channel to channel cross talk. This requires a .s8p or even a .s12p touchstone file.

But what about the TX and RX devices? IBIS models have been used to describe the TX and RX properties of devices which includes the switching rise time, output impedance, input gate capacitance, and even a simple RLC package model. However, in virtually all high speed link transceivers, equalization and clock recovery circuits are an integral part of the I/O circuitry. Up until now, there were no hooks in the IBIS model to include these features.

Extending IBIS models to include these “analog” features is the purpose of the IBIS-AMI(Algorithmic Modeling Interface) spec. The paper by Todd Westerhoff and his co-authors, presented at DesignCon 2010, “Predicting BER with IBIS-AMI: experiences correlating SerDes simulations and measurement,” provides a concise introduction to the features of IBIS-AMI models and some of the learning curve SiSoft and IBM went through to bring their simulation tools into excellent agreement.

This paper introduces the role of the AMI spec and alternatives to circuit simulation for link analysis. Under the IBIS-AMI umbrella, there are two parts to a link model: the passive channel, from the pads on the TX chip to pads on the RX chip and the serdes Tx/Rx analog characteristics. 

The impulse response of the channel, which can be obtained from the SDD21 response of the channel, can be used to predict the statistical properties of the eye directly, or with a convolution integral, calculate the transient waveforms at the receiver. No circuit simulation need be performed, just signal processing.

The second part of the AMI model is the algorithm to process the received signal. This can be how the impulse response is transformed by the equalizer into a new impulse response or how the transient waveform is processed by the equalizer. Even the behavior of how the clock recovery circuitry acts on the received transient waveform can be described in the algorithm.

The rest of this paper describes the correlation between IBIS-AMI models simulated in IBM’s internal simulation environment, which has been extensively verified with measurements, and the Quantum Channel Designer, the SiSoft link simulator environment. As seen in the figure above, at the end of their program, the agreement between the two simulation environments turned out to be very good.

If you would like a good introduction to IBIS-AMI models, this paper is a good starting place.

Next No Myths Allowed Webinar: Frequency Dependent Material Properties, so what?, Thurs, Feb 25, 2010, 1 pm EST. Free, but you must pre-register here.

Spring Institute of Signal Integrity Classes, April thru May 2010, San Jose, more info and online registration here.

One of my fun activities at DesignCon is getting to conduct 10-minute interviews with signal integrity stars. These are filmed by RealTime with DesignCon and posted on their website.

I did about 10 different interviews and other reporters with RealTime did another 20 or so interviews. If you missed DesignCon, or just want to see some of the new products, materials, tools and design solutions you might have missed, you’ll want to check out the posted interviews.

In particular, here are some of my favorites you’ll want to be sure to view:
Colin Warwick, Agilent, talking about their new 3D display. In addition to looking like a couple of really cool SI Dudes, we were able to see the results from a full wave EM field solver of current flow in a via field. With the LCD shutter glasses, and interleaved left-right screen being displayed on the monitor, it really did look like the vias were standing out in front of the screen. This 3D capability is embedded in Momentum and EMPro., able to show currents, fields and voltages.

 Joel Peiffer, 3M, talking about C-ply. 3M can provide thinner than 25 micron thick C-Ply laminates, sandwiched between copper planes. The dielectric is ground up Barium Titanate filled epoxy offering a Dk of 16-20. This is great for power and ground planes. The breakdown strength of the I mil core is more than 100 v. While Joel said these materials are in production and he has customers shipping their product with C-Ply, I could not get him to reveal any customer names. He just hinted that the early adopters are cell phone manufactures, and 10-15% of all cell phones are shipped with C-Ply.

Don DeGroot, CCN-I, talking about pcb materials measurements in his company. Don came from NIST, where he worked for 12 years as a researcher in the rf test group. He’s spun his experience in precision measurements into a company that performs contract materials measurements. He talked about the transitioning of NIST engineering techniques into a commercial business and how he does practical materials characterization.

Todd Westerhoff, SiSoft, talking about what’s new from SiSoft. At DesignCon 2010, SiSoft engineers gave 3 papers. One was on “When Shorter isn’t Better.” Todd described some problems where reflections in short tracks can cause problems, especially with resonances at specific lengths. If the traces are long enough some of these resonances may damp out and not be a problem. The danger, he says, in applying design rules is you may miss these length specific problems. This is why he advocates doing a post layout analysis.

To catch all of the RealTime interviews, check out their web site.

DesignCon 2010 is right around the corner. It will be a busy time for all. As you set your schedule for the fours days of the show, be sure to add these events to your list:

Visit beTheSignal.com at booth #319. You’ll want to pick up a mug, an Appendix A -pocket guide to signal integrity design guidelines and, of course, some chocolate! Stop by and meet Susan and Laura. And I may have copies of my science fiction book, Shadow Engineer, on sale.

Monday, Feb 1, in the Theatre, I will present a 3 hour education forum, “Practical Magic: Signal Integrity Problems Disappear with the Right Tools“. My Agilent buddies and I will be showing about a dozen demos of some really cool hardware and software tools that I think should be in every signal integrity engineer’s tool box. check out my youtube video!

Tues, 8:30 am, I will present a paper “Frequency Dependent Material Properties: So What?”, with Don DeGroot, Sanjeev Gupta and Colin Warwick. If you are wondering about all the hype associated with “causal material properties” and want to know how does this apply to me, you’ll want to check out this talk.

Tues, 9:20, my colleague, Paul Huray, will present, “Impact of Copper Surface Texture on Loss, a Model that Works.” There’s a lot of buzz these days about rms roughness of copper. Come hear Prof Huray explain it’s really the surface texture of the copper, not just the rms roughness, that affects the extra losses from rough copper. You may find, as I discovered, that “everything you know about current and signal propagation is wrong.” Come hear the right way of thinking about how signals really propagate on interconnects.

Tues, 3:45 pm, I will participate on a panel discussion, “Science Fiction…is it really fiction?” This has got to be one of the more fun events at DesignCon, at least for me. I get to share the panelist table with Gentry Lee, famed co-author with Aurthur C. Clark of the Rama series, among other books, and noted scientist at JPL. We will talk a little about our visions of the future and open up the floor to discussion. Rumor has it, some of us might have books available for a book signing!

Wed 8:30 am. If you missed my education forum on Monday afternoon, you can catch it again on Wed morning.

I’m exhausted already, just writing about the exciting happenings at DesignCon 2010. See you there!

I recently had a chance to don a pair of LCD shutter glasses and stare into a synthesized 3D image that popped out of the screen at me. Cascading colors flowed around obstacles. I could move my head around and see how the pattern of colors moved in and around the objects in the foreground.

No, this wasn’t a scene I witnessed in Avatar, which I also viewed in 3D IMAX, it was a demo of Agilent’s new 3D glasses incorporated in an upgrade to their popular Momentum field solver suite. I had a chance to sample the new 3D vision system at the FPGA Camp in San Jose on Nov 11, 2009. Wow! Pretty darn cool!

Tightly coupled into the Agilent’s ADS simulation environment are Momentum, which does 2.5 D full wave simulations and EMPro which does 3D full wave simulation. While both of these tools can show 3D perspectives of the static or dynamic, electric or magnetic fields or currents in and around conductors, the simulations seem to come alive when viewed in true 3D.

To make this possible, Agilent has teamed with Nvidia to leverage their high end GPUs for the visual processing. The 3D images are generated by projecting on the monitor an image for just the right eye, while synchronized with the opened right eye shutter on the LCD glasses, and then projecting the image for the left eye.

The frame rate is high enough so that you don’t perceive the flicker, but see the screen in true 3D, giving the sense of having the object, and its field distribution, projecting in front of the screen. I suppose the next step is to incorporate a 3D mouse pointer and be able to move it around to interact with the 3D environment.

If you want to learn more about this novel imaging feature, be sure to check out the webinar Agilent is providing on Jan 21, 2009. You can sign up at this link.

I can’t wait to find the right demos to use for my upcoming live classes. One of these days soon, if I hand you a pair of LCD glasses when you walk into the room, you’ll know what to expect.

Next public classes: Essential Principles of Signal Integrity and Advanced Signal Integrity Design, and Multi GigaBit Design, Sept 29- Oct 7 in San Jose, CA.

Next No Myths Allowed Webinar, “Selecting Capacitor Values for the PDN”, presented on Dec  9, 1 pm EDT.

I just learned from Colin Warwick, my buddy at Agilent, of a series of workshops Agilent is presenting on Fast Channel Simulation and Statistical Eye Diagrams.

If you do channel simulation and need to check very low bit error rates or need an accurate measure of the jitter distribution, you may have to simulate millions of bits. If you are also using the eye diagram simulation to explore design options, you may have 10 to 50 different designs to evaluate.  If you’re not doing it smart, you’re simulation is probably still running.

Agilent recently introduced some clever techniques based on the transient response of the channel and statistical analysis to synthesize eye diagrams for LTI (linear time invariant) systems which can show BERs well below 10^-12 in a few minutes of simulation time.

This process could revolutionize the way you explore new design options. To learn more about it, check out the workshop, coming to a city near you.

Our next No Myths Allowed webinar, May 6, 1 pm EDT, “S-Parameters, Signal Integrity and You”. Details and registration available at www.beTheSignal.com

Mike Resso, my long time collaborator of more than 15 years, and I have recently finished a book published by the IEC, “Signal Integrity Characterization Techniques“.

This book focuses on TDR and VNA measurement techniques and the use of S-parameters for signal integrity applications. We pulled together about 25 papers presented at DesignCon which Mike and I have authored or co-authored and supplemented them with five application notes I wrote for Agilent.

Unlike the papers, which are typically at an advanced level, these application notes start with the basics and explain, step by step how to interpret measurements in either the time or frequency domain and as either single-ended or differential signals.

If you deal with TDR or VNA measurements or need to know about S-parameters, this is a great resource. It will get you up to speed and enable you to understand the sophisticated measurements and analysis techniques used throughout the industry by the leaders in signal integrity.

We hope you enjoy it. Additional articles on this topic can also be found on my web site.

Mark your calendars for our next No Myths Allowed webinar, scheduled for Wed, May 6, 2009 at 1 pm EDT. Like all of our webinars in this series, it will last about 45 minutes with 15 minutes for Q&A and be well worth your time.

This one is entitled, “S-Parameters, Signal Integrity and You.” In 45 minutes, we will introduce the most important features of S-parameters, starting at the very beginning and exploring some of their features and why they are becoming the defacto standard to describe the high frequency behavior of interconnects.

I’ve started a list of the questions we will address in our brief 45 minutes. If you have another question important to you not on the list, drop me a note and I will consider adding it to the webinar. Here is what we will cover:

• What are S-parameters?
• Why should I care?
• Where do they come from?
• How are they simulated?
• How are they measured?
• How accurate are they?
• How do I look at them?
• What’s the deal with differential S-parameters?
• How do I measure differential S-parameters?
• What can I learn about an interconnect from them?
• What can I do with them?
• What are some of the common pitfalls I should watch out for?
• What are some of the resources I can leverage to get more value from S-parameters?

You must sign up by May 4th, in order to attend. We will send out an email note with the access information the day before the webinar. The webinar will be recorded and posted to our website, along with all our other video recordings, and available to all paid subscribers the day after the presentation.

Hope to see you in cyberspace!

A few years ago, I wrote a column about the then recently released EMC expert system, from IBM, EMSAT. At DesignCon 2009, I learned from Bruce Archambeault, a Distinguished Engineer at IBM and IEEE Fellow, who also happens to be the chief architect of EMSAT, that “every board at IBM goes through EMSAT.”

What could be a better endorsement of a tool than that? Maybe that IBM also requires all their OEM board design vendors to run their IBM specific boards through EMSAT and these vendors have integrated EMSAT into their design flow for all of their boards.

An EMC expert system is like having an EMC expert sitting over your shoulder making sure your board design doesn’t violate any of the more than 16 most important design rules to ensure passing EMC compliance tests.

The “secret sauce”, Bruce says, is not in what the rules are, which are freely shared (see below), but in the details of what constitutes a problem and what you do to fix the errors when you encounter them.

In addition to checking for EMC rule violations, EMSAT now also checks for some signal integrity problems. Below in one place is a handy check list of the various EMC and SI rules  EMSAT checks for in a board layout file. If you want more information about EMSAT, contact Gene Garat at Moss Bay EDA.

With permission from Bruce, here are the EMSAT rules:

EMSAT Rules

EMC

Signal Reference Rules

Critical Net Crossing Split Reference Plane: Critical nets must not cross a split in the adjacent reference plane.

Critical Net Changing Reference Plane:Critical nets must not change reference planes.

Net Near Edge of Reference Plane: Critical nets may not be within a specified distance of the edge of their reference plane.

Wiring and Crosstalk Rules

Critical Net Near I/O net: Critical nets may not be routed within a specified distance from an I/O net.

Length of Exposed Critical Traces: All critical nets must be buried between solid planes. The allowable length of the exposed portion of a critical net may be specified.

Critical Net Isolation (Single-Ended Nets): All critical nets must have empty space or  a “ground-guard” trace on either side of the critical net.

Critical Net Isolation (Differential Nets): All differential critical nets must have a “ground-guard” trace on either side of the differential pair of nets.

Critical Differential Net Length Matching and Spacing: All critical nets must be routed within a specified distance of each other, and the length of the differential pair of nets must match within a specified amount.

Decoupling Rules

Decoupling Capacitor Density: Decoupling capacitors must be placed between all adjacent plane pairs within a specified grid density.

Decoupling Capacitor Distance from IC Power Pin: A decoupling capacitor must be connected between the power and ground-reference planes and be placed within a specified distance from each IC power pin.

IC Power/Ground-Reference Pin Distance to Via: The trace connecting between the IC power and/or ground reference pin to the associated via to the power/ground-reference plane must be no longer than the specified distance.

Decoupling Capacitor Distance to Via: The trace connecting between a decoupling capacitor to the associated via to the power/ground-reference plane must be no longer than the specified distance.

Power/Ground-Reference Trace Decoupling: All power and ground-reference traces longer than a specified length must have a decoupling capacitor within a specified distance from the IC power pin.

Placement Rules

I/O Filter Net Distance: All I/O filters must be placed within a specified distance from the I/O connector.

Distance from Oscillator to Clock Driver: All Oscillators must be placed within a specified distance from the clock driver (or other device) that they drive.

Signal Integrity Rules

Net Integrity

Net Length: Report nets longer than a specified length.

Net Coupling: Signal Nets must not be routed within a specified distance of another signal net and not for longer than another specified distance. Optionally, Layer to Layer coupling can also be checked.

Length of Exposed Critical Traces: All critical nets must be buried between solid planes. The allowable length of the exposed portion of a critical net may be specified.

Net Stub Check: Check for stubs on a net longer than a specified length.

Critical Net Crossing Split Reference Plane: Critical nets must not cross a split in the adjacent reference plane.

Net Near Edge of Reference Plane: Critical nets may not be within a specified distance of the edge of their reference plane.

Via Integrity

Unconnected Via Pads: Unconnected Via Pads are not allowed.

Via Clearance Overlap: Via clearances must not overlap. Either the top and bottom layers, or all layers, can be selected.

Via -> Net Coupling: Signal nets must not be routed within a specified distance of a Via on another signal net. The distance between the Via and the Net must be clear. I.e., no intervening traces.

Via Stub Check: Check for stubs on vias. A via can have 2 violations. One for the stub above the highest connected layer, and one for the stub below the lowest connected layer. Vias that are connected together at the same physical location are combined together for the purposes of stub length calculation.

Decoupling Rules

Decoupling Capacitor Density: Decoupling capacitors must be placed between all adjacent plane pairs within a specified grid density.

Decoupling Capacitor Distance from IC Power Pin: A decoupling capacitor must be connected between the power and ground-reference planes and be placed within a specified distance from each IC power pin.

IC Power/Ground-Reference Pin Distance to Via: The trace connecting between the IC power and/or ground reference pin to the associated via to the power/ground-reference plane must be no longer than the specified distance.

Decoupling Capacitor Distance to Via: The trace connecting between a decoupling capacitor to the associated via to the power/ground-reference plane must be no longer than the specified distance.

Power/Ground-Reference Trace Decoupling: All power and ground-reference traces longer than a specified length must have a decoupling capacitor within a specified distance from the IC power pin.

For more information on this and other signal integrity topics, visit my web site, www.beTheSignal.com

There is an old joke about the guy who dropped a diamond ring on the ground one night. He’s down on his knees looking for it and another fellow comes along and asks to help. They’re both down on their knees for a few minutes with no luck. The stranger then says, “I can’t find it anywhere. Where did you drop it?”

The other guy says, “I dropped it over there,” pointing ten feet away. The stranger replies, “If you dropped it over there, why are you looking over here?” He replies, “Because the lights better over here.”

I think this story illustrates one of the limitations of traditional power integrity analysis. We tend to do what is easy, where the light is, rather than tackle the real questions, because they are hard.

Doing a simple SPICE simulation of the impedance profile of a collection of capacitors is easy, and every engineer should be doing this. But, taking the next step to explore the interaction of the capacitors and the planes, or how the mounting geometry influences the ESL and the resulting impedance profile, is hard. The only tool that will take into account the arbitrary, odd shaped power and ground planes, a fact of life in real world product design, is a 3D field solver.

While many of these tools have jewels of insight hidden within them, they are positioned ten feet away from most engineers, in the darkness. They are hard to understand, hard to use, hard to evaluate if the answer is correct or not, and take a while to spin through a lot of what ifs.

I think the recent announcement by Mentor Graphics at DesignCon 2009, of the release of HyperLynx 8.0, which includes power integrity analysis, now expands the circle of light into the power integrity world. Since its first release more than 15 years ago, HyperLynx has been an incredibly easy to use circuit simulator. With the inclusion of lossy line models and eye diagrams, it enables high speed serial link simulation to greater than 10 Gbps.

This easy to use interface and fast computation speed has been extended to power integrity analysis. Now it is easy to evaluate questions like, does position really matter? What is the impact of a Swiss cheese clearance hole field on the impedance of the decoupling capacitor? What is the impedance profile of the capacitors and the planes? Up to what frequency or rise time are decoupling capacitors really effective? For an odd, irregular shaped power plane, what is the DC resistance and are there any hot spots?

I’ve had the opportunity to take the beta version for a test drive and I think it will dramatically reduce the fear, uncertainty and doubt of designing the power distribution network in your design.