Eric Bogatin's Blog: What I Learned This Month

Getting started in signal integrity? check out the pdf copy of Chapter 1 from Signal and Power Integrity- Simplified, available for free download on www.beTheSignal.com

Getting started with IBIS-AMI models? read on….

You cannot predict the performance of a high speed serial link without having an accurate model for the transmitters (TX), the channel, and the receivers (RX). These days, the channel model, ultimately represented by its S-parameters, is the easy part.

If you can describe a single differential channel in terms of the S-parameters from one end to the other, you can incorporate it into most simulators. This could be a touchstone file with an .s4p extension, for example, signifying a 4-port S-parameter data set.

Even better, if you can include the S-parameters for one or two adjacent channels, you can include the impact from uncorrelated channel to channel cross talk. This requires a .s8p or even a .s12p touchstone file.

But what about the TX and RX devices? IBIS models have been used to describe the TX and RX properties of devices which includes the switching rise time, output impedance, input gate capacitance, and even a simple RLC package model. However, in virtually all high speed link transceivers, equalization and clock recovery circuits are an integral part of the I/O circuitry. Up until now, there were no hooks in the IBIS model to include these features.

Extending IBIS models to include these “analog” features is the purpose of the IBIS-AMI(Algorithmic Modeling Interface) spec. The paper by Todd Westerhoff and his co-authors, presented at DesignCon 2010, “Predicting BER with IBIS-AMI: experiences correlating SerDes simulations and measurement,” provides a concise introduction to the features of IBIS-AMI models and some of the learning curve SiSoft and IBM went through to bring their simulation tools into excellent agreement.

This paper introduces the role of the AMI spec and alternatives to circuit simulation for link analysis. Under the IBIS-AMI umbrella, there are two parts to a link model: the passive channel, from the pads on the TX chip to pads on the RX chip and the serdes Tx/Rx analog characteristics. 

The impulse response of the channel, which can be obtained from the SDD21 response of the channel, can be used to predict the statistical properties of the eye directly, or with a convolution integral, calculate the transient waveforms at the receiver. No circuit simulation need be performed, just signal processing.

The second part of the AMI model is the algorithm to process the received signal. This can be how the impulse response is transformed by the equalizer into a new impulse response or how the transient waveform is processed by the equalizer. Even the behavior of how the clock recovery circuitry acts on the received transient waveform can be described in the algorithm.

The rest of this paper describes the correlation between IBIS-AMI models simulated in IBM’s internal simulation environment, which has been extensively verified with measurements, and the Quantum Channel Designer, the SiSoft link simulator environment. As seen in the figure above, at the end of their program, the agreement between the two simulation environments turned out to be very good.

If you would like a good introduction to IBIS-AMI models, this paper is a good starting place.

Spring Institute of Signal Integrity Classes, April thru May 2010, San Jose, more info and online registration here.

This was the title of a panel on which I was invited to participate at DesignCon 2010. Of all my DesignCon activities, preparing and presenting at this panel was the most fun I had.

Joining me on the panel were Gabe Moretti, owner of GabeOnEDA, Charles Pfeil, engineering director at Mentor, and the author of the wonderful book, BGA Breakouts and Routing, available for free download, and Gentry Lee.

Gentry has a long list of professional accomplishments. He is a chief engineer at the Planetary Flight Systems Directorate at the Jet Propulsion Lab, previously in charge of the Viking Mars Lander program and active on other planetary explorer missions like Galileo. He is also well known for his ten year collaboration with Carl Sagan on projects like the Cosmos series.

In addition, he has an equally rich background as a science fiction author, collaborating with Arthur C Clarke for ten years on the Rama series of science fiction books, authoring a total of eight science fiction books.

Gentry started the panel session with the perspective that “science fiction is about all things that are not impossible,” as contrasted with fantasy which is “that which cannot happen.”

He sees three important trends happening now which will have dramatic impact, one way or another, on our lives within the next fifty years.   

“We are in the biological revolution era,” he said, where we will design life as we want it to be. We do genetic engineering on food and animals right now to optimize them for our needs. He suggested that we are very close to enabling genetic engineering of our children.

He can imagine a time in the not too distance future where a couple goes into a doctor’s office, leafs through a catalog of features (online, of course) to select the qualities of their child. Maybe they would select a boy, red hair, blue eye, IQ of 132, interested in geology, with a gift for language and will play the piano. For a price, parents could customize the child they want and have their genes modified for the features.

Of course, we will be able to tailor medicines specific for our own personal biology and change any specific genetic defects we might have using a customized viral probe. Will this grant us effective immortality?

But, in this future, where complete biological engineering is possible, who will be able to afford it? Initially, for sure, it will be expensive, so will this future only be for the rich? Will that leave the rest of us at a greater and greater disadvantage? If access to this incredible enabling technology is only to the rich, will this cause even more polarization and friction in our society?

The second significant trend he sees is the decline and fall of the US as an economic power. More and more manufacturing sectors have left or are leaving the US. Design jobs in these areas will inevitably follow and right behind it, research and development. There go the skilled jobs. What will this leave as the economy base for America?

He suggests that companies looking to develop design tools in the electronics industry would do well to be working with the countries that will have the future designers, which probably will not be the US.

Finally, he notes the third important trend to be the growing influence of virtual reality for kids today. A number of studies have come out in the last two years indicating that more than 10% of kids between the ages of 13 and 23 spend more than 50% of their awake time living in a virtual world. This includes not just World of Warcraft like virtual games, but also interacting on the web, immersed in facebook and online communities.

The young of today choose to spend their time in a virtual world rather than the real world. Unfortunately, it seems that it is usually the brighter students who are the ones we are loosing to virtual alternatives. Some of them say the real world takes too long. Why spend weeks building relationships in the real world when you can go through the complete cycle of meeting, falling in love and falling out of love with someone in hours in a virtual world.

Will this be the end of civilization?

Charles presented a great perspective on virtual tele-presence, such as currently provided by Cisco. While the technology may be in place, will it really be a substitute for building a relationship? Will it ever be really possible to add the human element to a tele-presence meeting? After all, it’s the relationship that is the prime basis of all interactions.

I presented a brief perspective on where I see the future of man- machine interfaces heading. It may not be too far in the future when we have a functional wet-ware interface, a direct brain and electronics interface. When that happens, I might sign up for some extra ram and maybe even a co-processor. I recorded my talk and posted a copy of the slides, which are available for free viewing from my web site.

A good time was had by all!

Next No Myths Allowed Webinar: Frequency Dependent Material Properties, so what?, Thurs, Feb 25, 2010, 1 pm EST. Free, but you must pre-register here.

Spring Institute of Signal Integrity Classes, April thru May 2010, San Jose, more info and online registration here.

One of my fun activities at DesignCon is getting to conduct 10-minute interviews with signal integrity stars. These are filmed by RealTime with DesignCon and posted on their website.

I did about 10 different interviews and other reporters with RealTime did another 20 or so interviews. If you missed DesignCon, or just want to see some of the new products, materials, tools and design solutions you might have missed, you’ll want to check out the posted interviews.

In particular, here are some of my favorites you’ll want to be sure to view:
Colin Warwick, Agilent, talking about their new 3D display. In addition to looking like a couple of really cool SI Dudes, we were able to see the results from a full wave EM field solver of current flow in a via field. With the LCD shutter glasses, and interleaved left-right screen being displayed on the monitor, it really did look like the vias were standing out in front of the screen. This 3D capability is embedded in Momentum and EMPro., able to show currents, fields and voltages.

 Joel Peiffer, 3M, talking about C-ply. 3M can provide thinner than 25 micron thick C-Ply laminates, sandwiched between copper planes. The dielectric is ground up Barium Titanate filled epoxy offering a Dk of 16-20. This is great for power and ground planes. The breakdown strength of the I mil core is more than 100 v. While Joel said these materials are in production and he has customers shipping their product with C-Ply, I could not get him to reveal any customer names. He just hinted that the early adopters are cell phone manufactures, and 10-15% of all cell phones are shipped with C-Ply.

Don DeGroot, CCN-I, talking about pcb materials measurements in his company. Don came from NIST, where he worked for 12 years as a researcher in the rf test group. He’s spun his experience in precision measurements into a company that performs contract materials measurements. He talked about the transitioning of NIST engineering techniques into a commercial business and how he does practical materials characterization.

Todd Westerhoff, SiSoft, talking about what’s new from SiSoft. At DesignCon 2010, SiSoft engineers gave 3 papers. One was on “When Shorter isn’t Better.” Todd described some problems where reflections in short tracks can cause problems, especially with resonances at specific lengths. If the traces are long enough some of these resonances may damp out and not be a problem. The danger, he says, in applying design rules is you may miss these length specific problems. This is why he advocates doing a post layout analysis.

To catch all of the RealTime interviews, check out their web site.

DesignCon 2010 is right around the corner. It will be a busy time for all. As you set your schedule for the fours days of the show, be sure to add these events to your list:

Visit beTheSignal.com at booth #319. You’ll want to pick up a mug, an Appendix A -pocket guide to signal integrity design guidelines and, of course, some chocolate! Stop by and meet Susan and Laura. And I may have copies of my science fiction book, Shadow Engineer, on sale.

Monday, Feb 1, in the Theatre, I will present a 3 hour education forum, “Practical Magic: Signal Integrity Problems Disappear with the Right Tools“. My Agilent buddies and I will be showing about a dozen demos of some really cool hardware and software tools that I think should be in every signal integrity engineer’s tool box. check out my youtube video!

Tues, 8:30 am, I will present a paper “Frequency Dependent Material Properties: So What?”, with Don DeGroot, Sanjeev Gupta and Colin Warwick. If you are wondering about all the hype associated with “causal material properties” and want to know how does this apply to me, you’ll want to check out this talk.

Tues, 9:20, my colleague, Paul Huray, will present, “Impact of Copper Surface Texture on Loss, a Model that Works.” There’s a lot of buzz these days about rms roughness of copper. Come hear Prof Huray explain it’s really the surface texture of the copper, not just the rms roughness, that affects the extra losses from rough copper. You may find, as I discovered, that “everything you know about current and signal propagation is wrong.” Come hear the right way of thinking about how signals really propagate on interconnects.

Tues, 3:45 pm, I will participate on a panel discussion, “Science Fiction…is it really fiction?” This has got to be one of the more fun events at DesignCon, at least for me. I get to share the panelist table with Gentry Lee, famed co-author with Aurthur C. Clark of the Rama series, among other books, and noted scientist at JPL. We will talk a little about our visions of the future and open up the floor to discussion. Rumor has it, some of us might have books available for a book signing!

Wed 8:30 am. If you missed my education forum on Monday afternoon, you can catch it again on Wed morning.

I’m exhausted already, just writing about the exciting happenings at DesignCon 2010. See you there!

Next No Myths Allowed Webinar, “Selecting Capacitor Values for the PDN”, Dec 9  2009, 1 pm EDT. Signup now.

In preparing for a paper at DesignCon 2010, I’ve been reviewing books and papers related to frequency dependent material properties and their effect on signal quality, especially at high data rates.

I’ve come across two excellent books that cover this topic, as well as many other advanced SI topics, better than any others I’ve encountered. They are Advanced Signal Integrity for High-Speed Digital Designs by Stephen Hall and Howard Heck and The Foundations of Signal Integrity by Paul Huray.

If you want to understand what characteristic impedance is, or why SSN is created by gaps in the return path of a signal, read my book, Signal and Power Integrity Simplified. But, if you want to trace the origins of signal integrity effects back to Maxwell’s Equations, read these books.

Advanced Signal Integrity for High-Speed Digital Designs by Stephen Hall and Howard Heck, is a bit of a sequel to Stephan Hall’s previous book, High-Speed Digital System Design. If you have this book, it is well worth upgrading to version 2.0.

Hall and Heck cover the traditional SI topics of E&M fields in transmission lines, reflections, cross talk and differential signaling. There is no coverage of PDN issues, but the sections on resistive loss, dielectric loss and equalization techniques easily make up for this.

In all of my searching, I found no better explanation of the Kramers-Kronig relation and how it drives the causal relationship between the resistance and inductance per length of a transmission line, or causal material properties. They describe the impact from RMS roughness on series resistance, even introducing the Huray model for copper surface texture.

The most useful section for me was on the models for the real and imaginary parts of the complex dielectric constant and the origins of the single, multiple and infinite pole Debye models. While this topic has been covered many other places, this chapter takes you from start to finish, giving you the tools to immediately apply this model to board design.

If you want to go the next step beyond Hall and Heck and re-calibrate your intuition about how to apply Maxwell’s Equations to Signal Integrity, you need to get Paul Huray’s new book, The Foundations of Signal Integrity.

In the interests of full disclosure, I freely admit that I have recently had the distinct honor and privilege of working with Prof Paul Huray on a project with a few Intel Engineers and have been able to “learn directly from the master.”

While another mentor of mine, Yuriy Schlepnev, the president of Simberian Software and architect of the 3D full wave simulator, Simbeor, has tried to teach me the right way to apply Maxwell’s Equations to signal integrity, I never spent enough time with him for his teachings to sink in.

From Prof Huray, I have finally learned what Yuriy has been trying to tell me:  “everything I know about the world is wrong.” It’s the fields that do everything and currents don’t really travel down a signal path. Carrying this concept of currents around, while a useful crutch, screws up our intuition about how RMS roughness really affects the series resistance of a transmission line.

Using his expertise in Maxwell’s Equations, Prof Huray has developed an analytical model for how signals are affected by the surface texture of copper which matches actual behavior well above 30 GHz. You will hear more about his approach at DesignCon 2010.

Prof Huray has condensed his years of teaching graduate level EM classes and his research programs which apply EM first principles to signal integrity problems into his latest book. This is not for the faint of heart. But, if you want to learn the right way of thinking about Maxwell’s Equations this is the book for you.

Since it’s the fields that really do all the work, he has color coded all reference to E fields in red and all reference to H fields in blue. The dramatic illustrations of the relationships between propagating E and H fields in waveguides, at boundaries and in various materials are tremendously valuable and also follow the color codes. This makes it much easier to follow the path from Maxwell’s Equations to their application in signal propagation.

Almost half of the book covers the very important topic of the role of material properties on signal propagation. As might be expected, he introduces the Huray model for copper surface texture and how this model can be extended to more irregular copper textures.

The serious engineer can find no better pair of books than these. Through their guidance you will be able to trace your way back to how, with Maxwell’s Equations and the right boundary conditions and material properties, all of signal integrity naturally flows. Their value will only increase with time as digital electronics encroaches more and more into the microwave world.

For information on this and other multi gigabit topics, check out our new class, Multi Giga Bit Design (MGBD).

Next No Myths Allowed Webinar, “Selecting Capacitor Values for the PDN”, Dec 9  2009, 1 pm EDT. Signup now.

The co-evolution of finer pitch packages and higher interconnect density circuit boards has enabled the explosion of mobile products for the consumer market, but is wrecking havoc in the test world.

More than 15 years ago, portable, consumer electronic products such as the hand held camcorder, drove the introduction of fine pitch packages, which have become known as chip scale packages (CSP). With pitches less than 20 mils (0.5 mm) and pad densities much higher than 100/square inch, conventional circuit board technology could not provide the cost effective, high density interconnect for this new generation of mobile product.

Higher density circuit board technology co-evolved along with CSPs. Multi layer build up or high density interconnect (HDI) or micro via substrates all use finer lines and smaller vias than traditional, mechanically drilled circuit boards. Every single cell phone manufactured today uses CSPs and microvia substrates.

While consumer products are well suited to leverage an interconnect form factor of finer pitch CSPs and higher interconnect substrates, the tester environment is not.

From the pin electronics of the tester to the pads on the chip being tested is a complex, Rube Goldberg hierarchy of interconnects. This system is designed to provide high performance electrical connections between thousands of pads on the pin electronics chips to thousands of pads on the die or wafer, and the flexibility of re-using most of the interconnects for thousands of different chip designs and millions of individual parts tested, while still allowing the pin electronics to be field upgradable.

The interface between the tester and the device to be tested is the load board. This is a massive space transformer circuit board. Pads on the bottom surface on 50-100 mil centers touch compliant pins connected to the tester electronics cabling or circuit boards. With more than 10,000 pins, even a 50 gm contact force per pin needs more than 1,000 pounds of force between the load board and the tester. It must be mechanically rigid which is why they are so thick. Typical thickness specs for load boards range from 150 to 200 mils.

To accommodate the more than 10,000 connections to the pin electronics, load boards have to be large, typically more than 15 inches on a side.

The electrical specifications for the load boards have to be higher performance than product boards. It’s not enough that the device works on the load board, the load board must have minimal impact on the signal quality of the device being tested so its intrinsic performance can be evaluated.

This translates to wider traces in controlled impedance with thicker dielectric layers. The long traces will often require more expensive, low loss dielectrics and multiple, solid, power and ground planes. These high performance interconnects are implemented with 16-30 layers of alternating signal layers and power and ground planes.

Load boards are driven by a different set of forces than product boards. They have to be large area, thick, many layers and use high performance, read more expensive, laminate materials.

On the top side of the load board are the connections to the device to be tested. Since the package already provides the space transformer from the die pad pitch to the circuit board pad pitch, historically, just a one to one compliant socket has been needed to interface the package under test to the load board.

As chip scale packages migrate to finer pitch, HDI substrate technology co-evolves to provide the higher interconnect needs. But the load board, with its large area, thick substrate and many layers cannot keep up. Here lies the challenge. How do you fabricate a load board, 200 mils thick, 18 inches on a side with 26 layers and have pads on the surface that can interface to a socket on 0.4 mm centers? And CSPs are migrating to even finer pitch.

While integrating a few HDI layers on top of a conventional load board to do the geometry transformation is being done, it is very expensive in direct cost and in yielded cost.

An alternative solution is to adopt the approach for testing a single die or whole wafer: add a space transformer from the fine pitch pads of the device to the coarse pitch pads of the circuit board.

After all, needle probe cards have been doing this for more than 40 years. Other technologies have evolved for wafer probing that use a ceramic substrate as the space transformer. In the Form Factor probe cards, for example, MEMs compliant tips are fabricated on the top of the ceramic substrate on pitches as fine as 2 mils. The pads on the bottom of the ceramic substrate interface to the load board with another compliant one to one interposer but on pitches of 50 to 100 mils.

This same approach can be implemented for final test of packaged devices. A daughter board acts as the space transformer from the finer pads pitch of the CSP to the coarser pad pitch of the load board.  A fine pitch socket technology is used on the top surface and a board to board interposer is used between the daughter card and the conventional load board.

An example of such an architecture, from R&D Circuits, is shown to the left.

Jim Russell, president of R&D Circuits says the cross over where this approach is lower cost than conventional load boards is for devices with 0.4 mm pitch and below. He goes on to say, “this architecture also allows the same, high value load board, to be used with multiple devices in a related family by just changing out the daughter card.”

In July 2008, R&D Circuit acquired Anestel Corporation which developed a board to board interposer based on patterned Kapton films with columns of silver filled silicone rubber. When compressed between two boards, this film is a one to one interposer. The typical connection pitch is 0.8 mm.

The daughter boards act as the space transformers. Being small size, few layers and high performance, they can ride the HDI wave and evolve with the finer pitch chip scale packages. They shield the load board from technology advances of the package devices, allowing the load board to be optimized for the tester environment.

Our thirst for higher performance, lower cost mobile consumer products will absolutely drive smaller, higher pad density devices, with a form factor indistinguishable from the chip. For load boards to keep up in final test it’s not surprising that the daughter card architecture currently used in wafer sort, should be adopted for package test.

see you in cyberspace!

Next No Myths Allowed Webinar, “Selecting Capacitor Values for the PDN”, Dec 9  2009, 1 pm EDT. Signup now.

“There ain’t no such thing as a free lunch,” is how the phase, popularized in Robert Heinlein’s book, The Moon as a Harsh Mistress, usually goes.

But that’s not how Scott McMorrow, director of engineering at Teraspeed, uses the phrase. He is fond of saying “There ain’t no such thing as a free launch.”

It’s sort of ironic, because he and his team are world experts at providing nearly free launches.

A launch is a transition from one transmission line geometry to another. While a coax cable and a stripline in a circuit board may each be electrically transparent, when one transitions into the other, the interface, or launch, will always show up as a discontinuity.

This discontinuity will cause a reflected signal and a reduction in the transmitted signal, which shows up in the insertion loss. The larger the discontinuity, the bigger the impact on the insertion loss. And, due to the physical size of a launch, it is always more of a problem at higher frequencies.

To minimize the launch discontinuity, Teraspeed recommends using a surface mount SMA connector and carefully optimizing the features of the launch via pad stack.

The figure to the left shows the TDR response of a conventional, well designed launch and a Teraspeed “free launch”, with a roughly 35 psec rise time signal and 5 Ohms per division. This was reported, most recently, at DesignCon 2009 and can be found in the reprinted article on the Simberian web site.

The pad stack includes the capture pads, the via barrel diameter, location of return vias, and clearance holes in any planes. Of course, what works in one board will be not always be the best design in another board due to the precise combination of signal layer and plane layer assignments and dielectric thicknesses.

Translating a specific board’s pad stack into the virtual world of a 3D field solver enables you to quickly optimize the clearance holes for a transparent launch. For example, if the launch impedance is high, make the clearance holes smaller. If the impedance is low, make the clearance holes larger.

This principle of a “free launch” applies to all transitions, especially important from the planar geometry of a circuit board to the 3D geometry of a connector.

Samtec made popular the term, “the final inch” to describe the break out region (BOR) of a circuit board connector’s via field. Using this principle of optimizing a few features in the immediate region of the launch, they can make the circuit board transitions into their connectors nearly transparent.

When done well, the transition from any connector to board traces can be transparent. This is important when designing test vehicles, ATE load boards and high performance product boards. As PCIe and USB enter the 5 Gbps and above regime, designing transparent launches will be an important skill.

For information on this and other multi gigabit topics, check out our new class, Multi Giga Bit Design (MGBD).

Hope to see you in cyber space at our next webinar!

Check out our next public classes: Essential Principles of Signal Integrity and Advanced Signal Integrity Design, Oct 11-14 in Hillsboro, OR.

Check out our next No Myths Allowed Webinar, “Stack-up Design for Differential Pairs”, presented free on Sept  16, 1 pm EDT.

A lossy transmission line screws up digital signals. A clean bit stream going into an interconnect can be jumbled and distorted by the time it comes out. This is all due to the frequency dependence of the line parameters: the resistance, capacitance, inductance and conductance per length. The spectrum of the input waveform is distorted by the interconnect.

To work around this problem, you do what you can afford in the interconnect design and materials selection. In addition, a revolutionary solution is to perform signal processing on the signal’s spectral content. This is implemented with pre- or de-emphasis and equalization. These techniques condition the spectrum of the signal to compensate for the spectral degradation by the interconnect. (These and similar topics are covered in our new class, Multi Giga Bit Design (MGBD))

It has long been known that there is one special waveform that is transmitted through an interconnect undistorted: a sine wave. Send a sine wave into a lossy interconnect and you get an identical sine wave coming out, though with an amplitude and phase change.

Sine waves are not distorted when transmitted through a lossy line.  But sine waves are not the only waveform that can propagate undistorted on a lossy line.

In 2002, Dr. Robert Flake, a professor in the Department of Electrical and Computer Engineering at Univ of Texas, Austin, realized there was another waveform that would propagate through a frequency dependent, lossy interconnect undistorted: an increasing exponential wave. He calls these waveforms, Speedy Delivery (SD). I’ve had the opportunity to meet with Prof Flake and discuss this intriguing effect.

Of course, no wave is going to increase exponentially forever, so it will always be truncated at some voltage level. This truncated exponential wave, when traveling through a lossy transmission line, will maintain its exponential shape. It is a property of the differential equation that describes the lossy line and the derivative properties of the exponential function.

Prof Flake generates his SD, truncated exponential pulses using an arbitrary waveform generator (AWG). He has sent pulses through 18,000 foot, cheap, twisted pair lossy transmission lines and found an exponential edge coming out, though attenuated.

The figure to the left is an example of a truncated exponential pulse as it enters a 200 m long RG58 cable (red), and then overlaid on the measured waveform as it comes out (black). The exponential shape is perfectly preserved, just shifted in time, with the non exponential part of the waveform attenuated and distorted.

Since the shape is preserved, the time delay of the edge through the interconnect can be very accurately determined. The fundamental time delay accuracy is related to the jitter in the AWG. Prof Flake has already demonstrated 2 psec accuracy in a time delay measurement over a 200 m lossy line.

This is an incredible observation. While the obvious applications are for accurate TDR measurements with lossy interconnects, such as long cable spools, heater tapes and power lines,  Prof Flake suggests this unique feature of exponential waveforms not being distorted by lossy interconnects may be useful in on-die applications or even lossy backplanes. It potentially could become as useful in overcoming the degradation from losses, in the future, as pre-emphasis and equalization are today.

Our next No Myths Allowed webinar, July 7, 1 pm EDT, “Link Analysis with Return Path Discontinuities”. Details and registration available at www.beTheSignal.com

On Tues, I walked the floor of the Sensors Expo in Chicago and came away with a new understanding of the coming importance of sensor “motes”.

Motes, small, remote sensor nodes as part of a larger network of distributed sensors, have been around for a while. Pictured at left is an example of a mote from Powercast.

At this conference, I saw a harmonic convergence of four technologies and two important killer apps that I think will accelerate the development and implementation of sensor motes.

Energy harvesting or scavenging, is the technology of taking “waste” or local fluctuations in energy from the environment and collecting and storing it in a battery or large capacitor for later use.

I saw a number of companies showing off savaging techniques, leveraging, random vibrations, using piezo-electric transducers which convert vibration into voltage, tiny wind turbines which convert a gentle breeze into electricity, thermopiles which convert a small temperature gradient into a voltage, small solar cells which convert low light levels into voltage and even rectifiers that harvest energy from the local EM noise.

The local storage is a small, typically either thin film or polymer based solid state rechargeable battery that could be recharged thousands of times. Regulating the energy conversion and the charging as well as the output voltage is a tiny, ultra low power ASIC chip.

This combination acted as a local power source for an ultra low power microcontroller, with power consumption measured in the microwatt range. TI was showing off their MSP430 series microcontroller with less than 1 microA standby current.

The microcontroller measures the output from a variety of sensors such as humidity, temperature, voltage, vibration, light level, proximity, rotation, tilt, B field, or acceleration.

Connected to the microcontroller and using the local power source is a micro power wireless transceiver, using either a Zigbee, 802.11x or even a proprietary standard.

This combination of four technologies enables a standalone, remote sensor node which, with the right software, can self-assemble into a highly linked network communicating between each other and a base station over long distances. Once set up, the node never needs servicing, never needs a battery changed, never needs replacement. They can be located in remote, inaccessible locations and forgotten.

The two applications that were talked about the most at the conference were environmental monitoring in commercial buildings and monitoring of the future smart power grid. Both applications apply to improving our energy efficiency. Given the number of nodes that might be used in a building and the number of buildings, and the number of nodes along the proposed smart grid, the unit volume of motes could be in the billions.

Will this technology be what fuels the next killer app for the electronics industry?

Our next No Myths Allowed webinar, May 6, 1 pm EDT, “S-Parameters, Signal Integrity and You”. Details and registration available at www.beTheSignal.com

Fiber weave induced skew in high speed serial links is a serious problem at 5 Gbps and above, but a new option from Dielectric Solutions may dramatically reduce this problem. Their solution, NovaSpeed 1080,  is a new low Dk glass fiber woven into a flatter fabric.

At IPC Expo last week, I had a chance to chat with John Kuhn, VP of Technology at Dielectric Solutions. You can watch my interview with him which I did for Real Time with IPC. This is a topic I’ve written on a number of times in the past. Here’s what I learned from John.

Glass weave induced skew arises when signals in the two lines that make up a differential pair travel at different speeds due to local variations in the dielectric constant they see. The dielectric constant variation is due to the higher dielectric constant of the glass weave, typically 6-7, compared to the resin, typically 3-3.5, and its bunching into fiber bundles. This is illustrated in the figure above.

If one line in a pair happens to be closer to a fiber bundle than its partner line, it will see a higher dielectric constant and travel slower than its partner. By the time the two signals come out the end of equal length lines, the slow path will be delayed compared to the faster path and there will be time delay skew between them.

This skew causes an asymmetry between the signals in the two lines and converts some of the differential signal into common signal, distorting the rise time of the differential signal, causing ISI, collapse of the eye and deterministic jitter.

In FR4 systems the typical glass weave skew varies depending on the weave pitch, the line to line pitch and the glass weave. While it may run to a worse case of 10 psec/inch, it may typically be 2-4 psec/inch. By its nature, the effect of glass weave skew is statistical.

The spec for the worst case acceptable skew is usually about 10% of a unit interval. At 5 Gbps, in PCIe Gen II, for example, the unit interval is 200 psec and the maximum acceptable total skew is less than 20 psec. This means that it is easily possible for the two lines that make up a differential pair to violate a skew spec after running only 5 inches or less.

It doesn’t mean no pairs will work longer than 5 inches. Weave induce skew is a statistical problem and depends on the random alignment of the signal track precisely over the worst case of the glass weave tracks. But, if you build enough boards with enough lines, some of them are bound to show excessive skew, and show a high bit error rate.

Fiber skew is one of the hardest problems to debug. Its signature is poor eye opening in one channel while an adjacent channel is just fine. Or, all the paddles cards in a collection might work but not in all combinations with a specific backplane. If you see these problems, suspect fiber weave induced skew as the root cause.

While there are a number of design based solution, a new technology solution is available that should be added to your tool box. Dielectric Solutions has introduced a new type of glass fabric which dramatically reduces the fiber weave skew effect. Their solution comes from two innovations.

They formulate their own glass, melt it down, extrude it into glass fiber and weave the fiber in a fabric. This gives them complete control over the entire glass fabric process. They’ve formulated a new low Dk glass with a dielectric constant of about 4.5, compared to the standard E glass with a dielectric constant of 6.8.

Second, they weave this fiber into a flat fabric so there is little lateral variation in the glass density. This combination means significant reduction in the glass weave skew. While FR4 and E glass combinations might show a maximum skew of 10 psec/inch, the worst case skew with the low Dk spread glass fabric is less than 1.6 psec/inch. This means much more margin in current systems, and enabling higher bandwidth systems when fiber skew sets the limit.

In the quest for higher bit rates and longer runs, the NovaSpeed fabric from Dielectric Solutions is an exciting alternative that can dramatically improve performance. One less problem for the high speed signal integrity engineer to worry about.

Hope to see you in Cyberspace at our next webinar!