Published by Eric Bogatin on 01 Dec 2009
11/29/09 Answer to last month’s pop quiz: “The total amount of bulk decoupling capacitance for a PDN rail should be selected based on the target impedance and…what else?”
Next No Myths Allowed Webinar, “Selecting Capacitor Values for the PDN”, Dec 9 2009, 1 pm EDT. Signup now.
This question is actually one of the topics covered in our upcoming webinar, mentioned above. Of course, the bulk capacitors are used to provide low impedance at a frequency where the VRM is no longer able to keep the impedance of the PDN below the target impedance.
How much bulk capacitance is required depends on the target impedance and this frequency. When the VRM impedance exceeds the target impedance, the impedance of the bulk capacitor (shown in red) had better be there to keep the PDN below the target impedance. This figure is from our Essential Principles of SI (EPSI) class.
Of the possible options, the correct answer is the second one, “the frequency where the VRM impedance is too high.”
This was a pretty easy question as most folks got it
correct. It is interesting that 25% selected the third answer, that the bulk capacitance depends on the loop inductance of the bulk capacitors.
The loop inductance of the bulk capacitors is important, as it will influence the parallel resonance with the ceramic capacitors, but it by itself will not determine how much bulk capacitance is required.
This whole topic of selecting capacitors- the number and their value- is very confusing, depends on a large number of system features and details and is difficult to generalize from what worked on one design to the next design.
That’s why we decided to cover this topic in the next webinar. I’ve collaborated with Larry Smith on this project, since he is one of my PDN gurus and I’ve learned a lot about PDN design from him. I hope you will join us on Wed, Dec 9, 2009. If you miss this live event, the webinar will be recorded and posted on our web site.
If you would like to get additional details on PDN design, you can also read the new chapter I wrote in my book, Signal and Power Integrity- Simplified.
And, if you are looking for a new challenge, check out the latest pop quiz we added to the web site!
I hope to see you in cyberspace!
It is interesting that only 42% of you got it correct! This means 58% got it wrong. This way of specifying differential impedance: a single-ended impedance and a differential impedance, is a common way of specifying line impedance. Now you know, it’s really specifying uncoupled lines, with a spacing about 3x the line width.
The general answer is that increasing the coupling will always decrease the differential impedance; but by how much? The only way to really know is with a 2D field solver. Because I’ve looked at similar problems a lot, I know the answer is somewhere between a 10% and 20% reduction in the differential impedance, but I can’t pin it down any finer without putting in the numbers with a field solver.
We had 325 answers to this quiz on our web site. More than half of you got the right answer, which was either 10% or 20%.
At 28%, the consensus was S11, followed by SDD11 at 23%. This is surprising, as neither answer is correct. This topic is covered in detail in the
cavity can be very large and long range.
The correct answer is False. 99.99% of all VNAs are single ended VNAs and they are perfectly fine at measuring differential S-parameters. With a little matrix math, the single-ended version can be converted into the differential version. This is valid for all linear, passive interconnects.
is “it depends”, it’s not always the best answer. In the case of transparent vias, the limitation is really the via stub. The correct answer is the fourth one, minimize the stub length, which 23% of you correctly answered.
As you can see on the results table to the left, most of you got the right answer. For those that want to understand this better, take a look at
As a rough approximation, the ESL of a capacitor is composed of three elements, the sheet inductance of the capacitor and surface traces, the via loop inductance to the top of the power and ground plane cavity and the spreading inductance in the power and ground plane cavity. Each of these can be estimated with simple approximations.
There were 303 answers submitted. Our web site assures that a person can submit only 1 answer. 70% of you got it correct.