What I Learned this Month

I’ve been teaching signal integrity for more than 20 years and keep getting asked the same questions over and over again. That’s one reason I wrote my text book, Signal and Power Integrity- Simplified.

I read so many on-line forums where engineers- both novices and very experienced, ask some very important fundamental questions, and the responders struggle or muddle through the answers.

I tried to include the answers to many of these questions in my book. Here is a short list of 20 questions which are answered in detail in my text book. If you puzzle over some of these signal integrity questions, you might find it instructive to browse through my text book.

1. Why are signal integrity problems only going to get worse as we progress on Moore’s Law? (section 1.7)
2. Why is the bandwidth of a signal related to 0.35/RT? (section 2.10)
3. What is the origin of the rule of thumb that the bandwidth of a clock signal is roughly the 5th harmonic of the clock frequency? What are the underlying assumptions? (section 2.13)
4. What is the difference between a “real” component and an “ideal” circuit element and why is this distinction important? (section 3.3)
5. What is sheet resistance and why is this an incredibly useful figure of merit? (section 4.5)
6. Why is the capacitance of a simple, short wire hanging in space about 2 pF? (section 5.2)
7. What really is inductance and how is it influenced by physical design? (section 6.3)
8. What is ground bounce and how can I reduce it? (section 6.7)
9. Why does current in a conductor re-distribute at high frequency? (section 6.16)
10. What does characteristic impedance really mean? (section 7.9)
11. How does return current really flow in a transmission line? (section 7.13)
12. How does return current flow from one plane to another when the signal transitions through a via? (section 7.14)
13. Why are there reflections? (section 8.2)
14. Do corners cause reflections and when should I care? (section 8.16)
15. Where does dissipation factor and dielectric loss come from? (section 9.6)
16. Why are the capacitance matrix elements sometimes negative? (section 10.6)
17. What is differential impedance and how is it different from odd mode impedance? (section 11.7)
18. Why is there no far end cross talk in stripline? (section 11.11)
19. Why are there always ripples in return loss and sometimes in insertion loss? (12.11)
20. What is spreading inductance and why is this important? (section 13.14)

I teach two classes in which I introduce essential principle #5, that whenever the instantaneous impedance the signal sees changes, a reflected signal is created. Almost without fail, at the end of the class, some brave soul, usually a younger engineer, comes up to me and asks that very important question, “Why?”

The flip answer is that if there were no reflected signal created when the instantaneous impedance the signal encounters changes, the universe would blow up. The reflected signal is created to keep the universe in harmony.

To see the problem, look at the figure to the left. The instantaneous impedance defines the ratio of the propagating voltage to the current in each region. If the instantaneous impedance in the two regions is different, the ratio of the voltages to currents in the two regions must be different.

Think about the incident voltage that hits the interface and continues to the other side. If there were no reflections, and the incident and transmitted voltages were different, there would be an electric field between two points on either side of the interface. The closer these two points get, the larger the electric field.

If we bring the two points really, really close but still sitting in the different impedances, the field could become extremely large, and the universe could blow up.

So, maybe the voltages have to be the same. But, if the impedances are different, the ratios of the voltages to the currents in the two regions have to be different different. If the voltages are the same, the currents into the interface must be different. But, if there is more current going into the interface than transmitted out, charge will build up and if we wait long enough, the universe will explode at the interface.

These two conditions, of the voltages being continuous and the net current into the interface being 0, are called boundary conditions. They cannot both be met without a reflected signal being created. The details of how the reflected signal helps to keep the universe in harmony and the derivation of the reflection coefficient and transmission coefficient can be found in the brief article I wrote for PCD&F magazine.

So we see that the most common signal integrity problem, the creation of reflections from impedance changes and the signal distortion that results from multiple reflections, is really a good thing. Without it, the universe would blow up.

Cross talk between two single-ended or two differential channels can be a problem which causes a product to fail. While a typical required signal to noise ratio (SNR) for some systems may be as low as 20 dB, in mixed signal applications it may be as high as 60 to 80 dB and in lossy channels, it may need to be above 45 dB.

To various extents, the coupling between aggressor and victim channels depends on the signal rise time, coupled lengths, interconnect density and line impedances. But not all system simulators take into account all the couplings which can cause problems. This is why it is sometimes important to measure the channel to channel cross talk.

S-parameters provide a natural way of characterizing cross talk between channels because each term in the S-parameter matrix really describes the coupling of one port into another. When the ports are on different channels, this is really the cross talk between the channels.

In the recently posted article on the Test and Measurement web site, “Use S-parameters to describe crosstalk”, Alan Blankman and I review the properties of S-parameters which make them so suitable to cross talk and some of the features to look for in both the frequency domain and the time domain.

If you care about cross talk, you’ll want to check out this feature article.

There are two clear trends in all high speed interfaces, such as PCIe, SAS, Infiniband and even DDR memory: data rates are currently in the gigabit regime and there is a roadmap that requires the current data rates to operate at even higher data rates in the next generation.

As we all know, as data rate increases, signal integrity effects get worse and luck goes down.

If you want to get some insight into the design strategies and tactics to manage the transition to the next higher data rate, you’ll want to watch this webinar I moderated in late Aug, 2012. This topic is one of the themes in our new class: Advanced Gigabit Channel Design (AGCD). For more information, check out our web site.

In my role as contributing editor for EDN, in this webinar, I moderated a panel of three industry experts: Jim Nadolny of Samtec, Brad Griffin of Cadence and Allen Tung of NXP. I posed them three questions about the problems, strategies and tactics of higher data rate system design and we discussed the answers.

There were a number of key points that came out. Here is a brief teaser.

Brad Griffin: for shorter time to the correct design, it’s critical to integrate analysis as part of the layout and design flow. This includes not just reflections, cross talk and losses, but also “power aware” analysis.

Allen Tung: USB 3.0 operating at 5 Gbps will see significant eye closure due to the losses in the boards and cables in typical applications. One way of opening eyes and minimizing the impact from the interconnects is adding a re-driver or repeater chip in the signal path, typically placed at the edge of the board. This does not require any changes to the rest of the circuit.

Jim Nadolny: As a good rule of thumb, the eye will probably be sufficiently open with no equalization if the insertion loss at the Nyquist is no more than –7 dB. There should be about 20 dB SNR so the acceptable cross talk should be less than about –25 to –30 dB in this case. Using pre-emphasis only, you can recover an acceptable eye with about –12 dB insertion loss at the Nyquist. And with FIR, CTLE and DFE, you can recover an acceptable eye with about –25 dB insertion loss at the Nyquist.

You can read a longer review of this webinar by Richard Goering, posted here. And, you can view the entire webinar, recorded and posted here.

If you have suggestions for future webinars, drop me a line!

“Most of the designs I get pulled into are really design rescues,” Jim Herrmann, Managing Partner & Principal Engineer at AppliedLogix, LLC, said at the 2012 IEEE EMC Global EMC and SI University.

From more than 25 years of hands on, practical design experience, Jim had an epiphany moment that the problems in all the designs he’s rescued have had four key root causes. He says, if you pay attention to these four key design concepts, you will avoid most of the signal integrity design problems in your next design.

Concept #1: Treat all interconnects as transmission lines and worry about their return paths as much as the signal paths. Always pay attention to the signal’s return path.

Concept #2: Try to engineer the transmission lines to look as close to a coax as possible, with the return path symmetrical around the signal path. Route in stripline, keep signals away form he edge of the board.

Concept #3: Forget the word “ground”. Board ground is just another piece of copper. Think “return path” and do everything possible to reduce the inductance of the return path.

Concept #4: Do everything possible to reduce the loop inductance of every element in the PDN. Drive out inductance in the PDN path.

Not a bad, concise list of important design guidelines to follow.

At the IEEE EMC Global EMC and SI University, Rick Hartley, a 47 year veteran of the circuit board design, SI and EMC industry, presented a short, personal account of a few of the more interesting problem boards he’s worked on over the years.

He offered a few gems of insight along the way.

“Its much easier to design a board that works the first time, and much harder to find a problem and fix it. Anything you do to fix a board after the fact is really just a band aid.”

“To control noise and EMI, we need to control containment of the electric and magnetic fields.”

He echoed the theme of the Global University: “Return paths are not just important, they are everything.”

When asked the difference between an SI problem and an EMC problem, he said, “An SI problem is when you step on your own toes. An EMC problem is when you step on someone else’s toes.”

Rick offered four examples of boards with problems, and the fixes which turned a crisis into a success.

Example #1: In a four layer board, low density board, the surface microstrip traces were referenced to a 5v plane, but no low impedance path was provided for the return current to get back to the 0v plane, connected to the driver.  He re-routed the adjacent plane to be the 0v plane, and EMI problem went away. Moral of the story: follow the return paths.

Example #2: In a high speed, multi layer board, the I/O section was carefully designed to minimize any common currents which could get out on the many 100 Mbps cables. As all the I/O were differential, the ground plane along the edge of the board was isolated from the board and only differential signals were allowed to cross the gap. But the board still radiated from the cables.

Then he noticed there were dozens of LED control lines that crossed the gap to light up the connectors. Even though they were “low speed”, they had just as fast an edge as the data. After adding low pass filters to the LED control lines, problem was eliminated. Moral of the story: “just because you think a line is low speed, doesn’t mean it is.

Example #3: “The best example of a the worst design.” The control board, with two processors and two memory banks was an 18 layer board. Many of the signal layers were filled with serpentines to keep the length skew between all the control to memory connections within 50 mils, even though the clock was 133 MHz.  To keep costs down, the 18 layer board had 4 signal layers between planes- difficult to control impedance and very high cross talk.

When he evaluated the timing, his team agreed that 300 psec was the timing skew they needed, which was a length skew of about +/- 1 inch. With this skew, the board routing could be reduced to only 10 layers, with two signals between planes, a more robust design. Moral of the story: overly tight constraints may increase the complexity of the board and introduce new problems.

Example #4: Taken from Lee Ritchey’s book, showed a 6 layer board, with large spacing between the power and ground planes, failing an EMC test. After copper fill was added to the signal layers, the board passed the radiated emissions test.

They say an expert is someone who has made all the mistakes possible. I always learn something listening to an expert. This is partly why this Global U is so valuable.

Every now and then, as I walk the floor of a trade show, a product or booth really catches my attention. At this show, I was stopped in my tracks when I saw the EMI Avengers, in battle with Evil EMI. Leading the Avengers was Eriko Yamato, as Wonder Woman.

Once she got my attention, her gentle, persistent tug would not let me go until I learned about the latest product Tech-Dream added to their distribution list, EM-ISight. This is a new near field scanning tool which moves a robotic arm in 3D around the surface of a functioning board, “sniffing” the near field at frequencies from 10 kHz to 40 GHz.

Hotspots in the local electromagnetic field at any frequency can be mapped over the product surface and even superimposed over a photo of the product to identify potential high field regions.

Of course, as Eriko points out, it’s always important to not confuse the near field with the far field. Sometimes a local near field hotspot is just a local hot spot and does not contribute to radiated emissions.

But a tool like the EM-ISight will give you a new window into the currents flowing on your board. And more information is always a good thing.

The second instructor at the IEEE Global EMC and SI University was Prof Tzong-Lin Wu, of the Dept. of EE, National Taiwan Univ. He flew in from Taiwan last night on a 22 hour flight to be here in Pittsburg, and showed no signs of jet lag.

While most of his presentation was setting the foundation of transmission line theory, he also spent time talking about return paths. This is the growing theme for this Global University. In particular, he offered a pop quiz to the 50 attendees.

He provided four different routing cases and asked our group, what would be the rating of each routed case, from best case to worst case?

Of course, the two extremes are obvious. Case 1 will be best and case 2 will be the worse.  After all, it’s important for the signal to never cross a split in the return path. But what about case 3 and 4? Which is worse, and by how much worse?

Our intuition may suggest that case 4 will be much worse than case 3. If the return path sees a continuous return, there should be little radiated emissions. So, shouldn’t case 3 be much better than case 4?

To show the impact of these four cases, Prof Wu shared simulations and measurements he has his students do at National Taiwan University.

Each of these four cases were built  in simple circuit boards and the radiated emissions measured by students. Their results are shown here.

Case 2, the signal crossing the gap, shows the most radiated emissions.

Case 4, with the signal hopping over small squares of holes in the return plane, creates the next most emissions. This was sort of expected. What is really interesting is that the case 1 and 3, with a continuous return plane, are identical. This says, even though there were gaps in the return path, but outside the width of the signal line, the gaps played no role in radiated emissions. It only takes a little web of continuous return path under the signal line to control the radiated emissions.

This was a great example of the dance between theory, measurement and simulation to illustrate the importance of return paths.

“Not all EMC rules are created equal,” Bruce Archambeault, a distinguished engineer at IBM and industry icon introduced as the theme of his tutorial at the Global University.

New to this year’s Global University is a focus on signal integrity in addition to the traditional EMC topics. About 60 engineers attended the 16 different tutorials from industry experts.

In the first session was on PCB Layout for EMC Compliance. The subtitle for Bruce’s session was really, “All about inductance and return paths.”

Bruce started out challenging us to question the relative importance of some of the many design rules we use in board design. “Should decoupling capacitors be close to the chip?” Yes, he says, but this is not the most important rule to pay attention to.

Instead, he says, paying attention to return paths of signals and the inductance of each path is probably the most important design rule to follow. The loop inductance of signal-return paths influence the switching noise in all high speed systems.  He went on to illustrate this principle by describing how geometry influences loop inductance and routing traces on aboard to control and minimize loop inductance.

Like a doctor who only sees patients with a medical problem and rarely talks to healthy people, I see hundreds of examples of S-parameter files either from measurements or simulations, all with some sort of problem.

I find one of the most common problems with these files is the port assignment. With four or more ports, there are multiple ways of labeling the ports. Two options are illustrated to the left.

While the quality of the information stored in the S-parameters is unaffected by the port labeling, how we interpret each S-parameter matrix element is strongly affected by the port labeling scheme.

For example, in one assignment, the insertion loss is the S21 matrix element, while in the other port assignment, the insertion loss is S31.

If you generate your S-parameter file using one assignment, but it is interpreted by someone else with the other port assignment, the analysis will be incorrect. Unfortunately, because so few users of S-parameters know what to look for in the S-parameters or are so afraid of looking at the actual data stored in the touchstone file, rarely is this root cause ever identified until too much time has been wasted.

Instead, I get a frantic call that the measurement and simulation is off, or that the eye predictions for a channel are completely collapsed, or that the model from their connector or package vendor shows that the signal is too small getting through the channel and how should they re-design the channel.

Following a few simple guidelines, this simple and common problem can be identified before it becomes a real problem and completely eliminated.

For more information on quick fixes to this problem, please see the paper that Alan Blankman and I wrote for Test and Measurement World, or check out the SPSI class I teach, which goes through this analysis in much more detail.