Eric Bogatin's Blog: What I Learned This Month

Getting started in signal integrity? check out the pdf copy of Chapter 1 from Signal and Power Integrity- Simplified, available for free download on www.beTheSignal.com.

Inductance is probably the most confusing topic in signal integrity and one of the most important. It plays a significant role in reflection noise, ground bounce, PDN noise and EMI.

Since this topic is not taught in school in a way that is at all useful to help solve signal integrity problems, practicing engineers are force to learn about this critical topic from professional development courses, books or articles.

Two inductance books are now available which should be on every engineer’s bookshelf.

The original definitive book on inductance, Inductance Calculations, by Fredrick Grover, first published in 1946, is now available as a reprint. The newest book, Inductance: Loop and Partial, by Clayton Paul, was just released in 2010. These two books cover calculating partial and loop inductance of conductors in a wide variety of geometries. The approximations offered are both immediately applicable to calculating inductance values for cable, connector, packages and circuit board interconnect structures.

Inductance Calculations was published in 1946 by D Van Nostrand CO. It was then reprinted by Dover in 1948 and was out of print by the mid 1980s. It was just re-printed this year and is now available from Amazon in paperback for a very low price.

Motors, generators and rf components experienced a period of high growth in the 1940s. At their core were inductors and being able to calculate their self and mutual inductance using pencil and paper was critical (before the use of electronic calculators). While many coil geometries had empirical formulas specific to their special conditions, Grover took on the task of developing a framework of calculation that could be applied to all general shapes and sizes of coils.

While he did not explicitly use the term, what he calculates in his book are really partial inductances, rather than loop inductances. There is a raging debate in the industry today about the value of this concept.

Proponents say it dramatically simplifies solving real world problems and is perfectly valid as a mathematical construct. You just have to be careful in translating partial inductances into loop inductances when applying the concept to calculate induced voltages.

Opponents say there is no such thing as partial inductance, it’s all about loop inductance and if you can’t measure it, you should not use the concept. There is too much danger of misapplying the term.

Inductance: Loop and Partial, goes the next step in putting partial and loop inductance in perspective. Both terms are clearly articulated and defined. Many of the formulas Grover introduced are presented in Paul’s book, with the added benefit of the details of the derivations shown. In particular, the methods of combining partial inductances in parallel and series is introduced to show the connection between loop and partial inductances.

As Clayton Paul points out, there are many cases where partial inductance is an easier approach to solving inductance problems. In a pin field connector, for example, the return path may not be defined until after the pins are connected up in the circuit. Using the partial inductance matrix values makes this an easy circuit to simulate, while using loop inductance matrix values is a more complicated solution.

I personally am a big fan of partial inductance, and use it extensively in my book, Signal and Power Integrity- Simplified. It makes understanding the concepts of inductance easier, and highlights the three physical design terms that reduce the loop inductance of a signal-return path: wider conductors, shorter conductors, and bringing the signal and return conductors closer together. Most importantly, partial inductance is a powerful concept to aid in calculating inductance for arbitrary shaped conductors.

Inductance is fundamentally the number of rings of magnetic field lines around a conductor, per amp of current through it. In this respect, it is a measure of the efficiency for which a conductor will generate rings of magnetic field lines. To calculate the inductance of a conductor, it is a matter of counting the number of rings of field lines and dividing this by the current through the conductor. Counting all the rings surrounding a conductor is really performing an integral of the magnetic field density on one side of the conductor.

Literally everything about the electrical effects of interconnects stems from Maxwell’s equations. Paul and Grover start from the basic Biot-Savart Law, which itself comes from Ampere’s Law and Gauss’s Law, each, one of Maxwell’s equations, and derives all the approximations for various geometries. The Biot-Savart Law describes the magnetic field at a point in space from a tiny current element.

Using this approach, the authors are able to calculate the magnetic field distribution around a wide variety of conductor geometries and integrate the field (count the field lines) to get the total number of rings per amp of current. Using clever techniques of calculus, they are able to derive analytical approximations for many of these geometries.

The advantage of Pauls’ book is that the hidden steps in many of the derivations are outlined. Luckily, we don’t have to do the derivations ourselves, but can rely on the work of experts and we are then in a position to use the results.

A commonly used approximation is for the partial self inductance of a long straight, rectangular conductor, such as a lead frame in a QFN package or a connector pin. It is calculated as:

nH

Where
L = the partial self inductance in nH
B, C are the thickness and width of the conductor cross section in inches
Len = the length of the conductor in inches.

For example, for a 1 inch long lead, 3 mils thick and 10 mils wide, the partial self inductance is 23 nH. This is roughly 25 nH per inch, or 1 nH/mm, which is a common rule of thumb for the partial self inductance of a wire.

If you deal with connectors, packages, vias, board discontinuities or odd shaped transmission lines, and need to estimate the loop inductances of non uniform sections, these two books will be essential resources. You will have a great collection of inductance approximations at your fingertips.

Getting started in signal integrity? check out the pdf copy of Chapter 1 from Signal and Power Integrity- Simplified, available for free download on www.beTheSignal.com

Today, signal integrity has become the limiting factor in all products operating at 200 MHz and above. This includes all communications products, servers, personal computer and even cell phones. Not paying attention to signal integrity in the beginning of a design means the product may not work at bring-up.

While the highest end applications- telecommunications, test and measurement, super computers, mainframes and servers have been in this regime for more than thirty years, mainstream consumer products have been sensitive to signal integrity effects for only about ten years.

At the dawn of the “mainstream signal integrity” era, before “social networking” was even imagined, there was the SI-List. Almost all signal integrity engineers, at one time in their career, have participated on this email distribution list, either posting questions, answering questions, participating in the debates or listening to the chatter.

Sixteen years ago, on May 16, 1994, the SI-List was born with 30 members on the charter email list.

Ray Anderson, then a recent convert to signal integrity from years as a microwave engineer, came up with the idea of an email discussion group to continue the question and answer period from the last day of a four day short course he had taken on signal integrity.

He had recently joined Sun Microsystems as a signal integrity engineer. His jump start into this new field was “Electrical Modeling, Simulation and Design of Electronic Packages”, taught by Raj Mittra, Paul Franzon and Jose Schutt-Aine in San Jose, CA on May 9-12, 1994.

“On the last day of class I said it would be really neat if we put together a mail list to pose questions and answers to continue the discussions. I went back to my office on Monday and hacked together an email list on the SPARC2 worskstation sitting in my office at Sun Microsystems with the thirty names from the class.”

Figure 1. Ray Anderson in his package characterization lab at Xilinx, where he is currently a senior engineer.

Sixteen years later, there are 4,000 members on the SI-list spread over more than 34 countries. The range of participants starts with novices and students in college and extends to world renown experts such as Scott McMorrow, Steve Weir, Istvan Novak and Todd Hubbing.

“The typical questions posed to the list today, are not that different from the early days,” Ray says. “Over the 18 years I’ve been in signal integrity, the technology has changed, but the physics hasn’t.”

The questions posed on the SI-list are an indication of the most confusing or controversial topics in signal integrity. Power distribution design (PDN) has always been a hot topic. How many and what value decoupling capacitors do I need on my board and where should they be placed are the most common questions asked, followed by what is the inductance of a via?

Questions range from general, open ended topics, such as which is better a VNA or TDR? to specific design questions about the timing delay between data and clock in the DDR3 JEDEC timing spec.

The hot topic these days include the frequency dependence of the dielectric properties of laminates and the use of S-parameters to describe interconnect performance including causality and passivity.

“When I started the list and saw it grow so fast, I had visions of herding cats. But, it has turned out to be remarkably well self managed. Peer pressure usually establishes the norms for behavior,” Ray says.

In addition to questions and technical discussion, it is also a bulletin board for announcements about upcoming webinar, seminars, short courses or job announcements. List etiquette discourages recruiters from posting job openings in the SI field, except by the hiring manager directly.

There are always those who abuse the list. However, over the 16 years of its existence, there have only been 12 individuals banned from the list. One of the biggest frustrations with long time participants of the list is with the same, fundamental questions being asked by “newbies.”

“If you are going to ask a question,” Ray advises, “do your homework first. Make an attempt to solve the problem yourself. Read some books, search the web and the list archives, then pose the questions. Don’t just try to get someone to do your work for you.”

To subscribe to the SI-List, go to : http://www.freelists.org/webpage/si-list

To view the archives of postings, go to: http://www.freelists.org/archive/si-list/

In the US, there are only a few conferences with a strong signal integrity theme. The value of attending a conference is not just to hear first hand about signal integrity design topics, but also the chance to mingle with other SI enthusiasts and see the latest solutions from vendors in this industry.

While it is possible to read a paper from the proceedings, there is much higher value in attending events where we can meet and greet. We often gain just as much when talking to another expert, as when discussing a design issue with a novice, or even a vendor.

DesignCon is the only conference specializing in SI. There are a few smaller events such as the EPEP conf, the Penn State SI Conference, and symposia such as the one I did with the IEEE EMC in Huntsville, Al. Some vendors put on their own one day events, such as CST, Agilent and Mentor.

There is now a new opportunity to add to our list. The IEEE MTT organization has been quietly building a presence in the SI world. Every year at the annual conference, the MTT usually has a one day workshop focusing on SI. These tend to focus on issues important at the very high frequency end- 5 GHz and above. I’ve had the privilege of presenting at many of the previous ones.

This year, Mike Resso and Brett Grossman have pulled together a sterling collection of presentations for the Signal Integrity Workshop, WSE, to be held on Sunday, May 23, 2010 at the Anaheim Convention Center.

The eight presentations planned are:

1. Paul Huray, University of South Carolina
“Bridging the Gap”

2. Michael Hill, Intel Corporation
“Microprocessor Power Integrity – Metrologies and Future Challenges”

3. Heidi Barnes, Verigy
“The Art of VNA Calibrations for Measuring Low Loss PCB Components”

4. Matthew Claudius, Intel Corporation
“End Use Model Correlation”

5. Bob Schaefer, Agilent Technologies
“Comparison of Fixture Removal Techniques for Connector and Cable Measurements”

6. Jim Rautio, Sonnet Software
“Measurement and Analysis of Substrate Dielectric Constant Anisotropy”

7. Evan Fledell, Intel Corporation
“Passive Interconnect Frequency Domain Characterization for Mixed-Medium and Vertical Interconnect Systems”

8. Leung Tsang, University of Washington
“Electromagnetic Modeling of High Speed Vertical Interconnect on Chip-Package-Board”

If you are involved in SI, I know you will find this program to be of great interest.

Next No Myths Allowed Webinar: Frequency Dependent Material Properties, so what?, Thurs, Feb 25, 2010, 1 pm EST. Free, but you must pre-register here.

Spring Institute of Signal Integrity Classes, April thru May 2010, San Jose, more info and online registration here.

One of my fun activities at DesignCon is getting to conduct 10-minute interviews with signal integrity stars. These are filmed by RealTime with DesignCon and posted on their website.

I did about 10 different interviews and other reporters with RealTime did another 20 or so interviews. If you missed DesignCon, or just want to see some of the new products, materials, tools and design solutions you might have missed, you’ll want to check out the posted interviews.

In particular, here are some of my favorites you’ll want to be sure to view:
Colin Warwick, Agilent, talking about their new 3D display. In addition to looking like a couple of really cool SI Dudes, we were able to see the results from a full wave EM field solver of current flow in a via field. With the LCD shutter glasses, and interleaved left-right screen being displayed on the monitor, it really did look like the vias were standing out in front of the screen. This 3D capability is embedded in Momentum and EMPro., able to show currents, fields and voltages.

 Joel Peiffer, 3M, talking about C-ply. 3M can provide thinner than 25 micron thick C-Ply laminates, sandwiched between copper planes. The dielectric is ground up Barium Titanate filled epoxy offering a Dk of 16-20. This is great for power and ground planes. The breakdown strength of the I mil core is more than 100 v. While Joel said these materials are in production and he has customers shipping their product with C-Ply, I could not get him to reveal any customer names. He just hinted that the early adopters are cell phone manufactures, and 10-15% of all cell phones are shipped with C-Ply.

Don DeGroot, CCN-I, talking about pcb materials measurements in his company. Don came from NIST, where he worked for 12 years as a researcher in the rf test group. He’s spun his experience in precision measurements into a company that performs contract materials measurements. He talked about the transitioning of NIST engineering techniques into a commercial business and how he does practical materials characterization.

Todd Westerhoff, SiSoft, talking about what’s new from SiSoft. At DesignCon 2010, SiSoft engineers gave 3 papers. One was on “When Shorter isn’t Better.” Todd described some problems where reflections in short tracks can cause problems, especially with resonances at specific lengths. If the traces are long enough some of these resonances may damp out and not be a problem. The danger, he says, in applying design rules is you may miss these length specific problems. This is why he advocates doing a post layout analysis.

To catch all of the RealTime interviews, check out their web site.

what’s new on beTheSignal.com:
Spring Institute of SI Training Classes now open for registration
Two No Myths Allowed webinars available for free viewing

Henry Ott is one of the gurus of EMC and noise control. After retiring from a distinguished thirty year career at Bell Labs, Whippany, he started a new company to focus on EMC education and consulting. For years, he has shared his practical expertise in electronic circuit design with the rest of us.

I first learned about correct cable shield termination for low noise design from his classic book, Noise Reduction Techniques in Electronic Systems, which he wrote in 1976. If you missed this classic of EMC design, it’s not too late.

His latest book, Electromagnetic Compatibility Engineering was just published by Wiley in 2009. While it includes much of the content of his first book, it’s been updated and more than half the book is brand new information.

I recently had a chance to chat with Henry about his book and about splitting planes and stack up design. The interview is part of the Shaughnessy Report on PCBDesign007.

“When is it appropriate to split ground planes?” I asked him.

“Never split ground planes unless you absolutely have to,” Henry said. “You have to have some external reason, not because you’re just laying out a board; for example, like a low leakage application in medical applications.”

“If you split ground planes and there is no compelling reason, the performance could be worse. I often fix problems my clients have by making the ground planes solid. 98% of the time, tie all the grounds together with a solid ground plane.”

An entire chapter of his new book is devoted to recommendations for circuit board stack ups. He evaluates 1, 2, 4, 6, 8, 10 and even 12 layer stack-ups to analyze the tradeoffs. There is sometimes more than one stack up that will work, but some might have higher performance margins than others. To select the best stack up for your application, you have to know the criteria for what is “better”. He offers six considerations:

1. a signal layer should always be adjacent to a plane
2. signal layers should be tightly coupled to their adjacent planes
3. power and ground planes should be closely coupled together
4. high speed signals should be routed on buried layers and located between planes
5. multiple-ground planes are very advantageous
6. when critical signals are routed on more than one layer they should be confined to two layers adjacent to the same plane.

If you work in signal integrity or EMC design this is a must have book. It has something for everybody.
 
One of the features that distinguishes this book from many others on the same subject is the inclusion of questions at the end of each chapter. While this of itself is nice, even better is that the answers are in the back of the book, in appendix F.

For example, question 12.8 is, “If a small circular and a small rectangular loop both have the same area and carry the same current at the same frequency, which will produce the greater radiated emissions?”

For the answer, you’ll have to check Henry’s book.