What I Learned this Month

“At 25 Gbps, everything makes a difference,” Dave Dunham told the crowd gathered for the 2nd Front Range Signal Integrity Seminar Series held in Longmont, CO on May 9, 2013.

Dave, the Director of Signal Integrity Engineering at Molex, outline the process Molex uses in designing connectors for ultra high speed, where simultaneous mechanical and electrical requirements push the envelop of what is practical.

He outlined a five step process and walked through a few examples.

The first step is establish a few simple figures of merit or rules of thumb. For example, usually the design goal is at the Nyquist frequency of the application data rate. The specs for return loss are typically less than –12 dB and for near end cross talk, less than –40 dB.

The second step is generating concept mechanical and electrical models. These are the basis for stress-strain curves and initial electrical performance.

The third step is feedback from all the team- mold engineering, stamping, assembly tooling, plating and marketing. This cycle of concept design- multi-disciplinary review feedback and re-design, continues a few cycles until a near final design converges.

In the fourth step, the final design is released. This is the best approximation to what will deliver the performance, reliability and manufacturability requirements. When it costs more than $100k for a mold to test out a design, simulation analysis tools are leveraged to explore virtual prototypes, rather than using the build it and test it approach.

This means it’s important to have confidence in the analysis tools that they will accurately predict the measured performance of a part once built. A design of experiments (DOE) study of the virtual prototype is a key element. This identifies the most important design variables and where attention needs to be focused for robust manufacturing.

The fifth and final step is verifying the design and creating the deliverables. For many customers, the board design is just as important in determining the connector performance as the connector itself. Dave’s team provides engineering support to help customer optimize the board design based on the specific details of the connectors.

If you would like to hear the details of how Dave implements this process for the highest performing connectors in the Molex portfolio, you can watch the complete recording and download a copy of his slides on the www.beTheSignal.com web site.

While  you are there, you can also watch the recording of Jeff Loyer’s presentation from March 7, 2013.

If you are in Longmont, join us for the live Front Range Signal Integrity Seminar Series. All these events are always free. I hope to see you there!

With the decline of print media, it’s sometimes hard to find quality feature articles that have high value technical content on topics related to signal integrity.

The experts who write many of these papers are still out there, but they are posting their white papers, application notes and presentations on their own web sites. I’ve started collecting links to these experts’ pages as a resource to identify top quality papers on signal integrity. You can find the list here.

This is a new landing page on my blog web site with a list of the experts, their web sites and some of the companies with a large selection of webinars and application notes available for viewing.

If you think I missed a good resource, please drop me a note offline and I will be happy to consider adding it to my list.

My latest feature article posted on the Test and Measurement World web site and the EDN Online web site, offers an example of how to characterize a high density interface.

In this  project, I worked with Gordon Vinther at Ardent Concepts. They have a pretty cool interface, the Omniprobe-R, that enables contacting an array of micro coax cables to any footprint, like a BGA.

This can be used to either test an active BGA in a load board test application or when it is attached to a product board.

Their interposer technology can also interface between an array of coax cables and a high density array of pads on a circuit board. This sort of technology is essential when testing motherboards with high speed serial links.

In our paper, we looked at the high speed performance of two cable interfaces connected together with their compliant interposer. The 4-port measurements were done to 20 GHz using a Teledyne LeCroy SPARQ. We walk through these measurements and show how to interpret the results and display them in a way to get immediately useful information.

The punch line is that the Ardent interposer is pretty darn transparent. Check out the feature article for the details.

If you want to learn more about interpreting S-parameter measurements, you’ll want to check out the next S-Parameters for SI 2-day class we have coming up in late Feb 2013. Hope to see you there!

It’s easy to measure S-parameters. It’s challenging to measure them without introducing artifacts and interpret the measurements correctly.

Our newest class, Hands on Workshop for S-Parameter Measurements (HOW-SPM), was created to teach these valuable measurement and analysis skills. We just finished our first class and it was a wonderful success.

This class was limited to only 12 students and filled up in the first 2 weeks after it was posted. Our next class on March 1, will also fill quickly.

Pairs of students shared a SPARQ, Signal Integrity Network Analyzer from Teledyne LeCroy, operating up to 40 GHz. All the principles and techniques we taught applied to ANY VNA. We limited attendance to 12 students total, so that everyone would get stick time and individual attention from our expert instructors. During the course of the day, everyone measured a variety of samples, each illustrating different measurement and analysis principles.

Resistors were used to illustrate how the measurement from a DMM at DC translated into the same resistance as obtained with a 40 GHz VNA- in the frequency and time domains.

A range of quality level 50-Ohm cables were measured to show the wide difference in bandwidth of good and bad cables, and the role of the connectors. We used port re-normalization to change the port impedances to view 75 Ohm cables and de-embedded the launches to show the impact at low frequency from the the port impedance, and the influence at high frequency from the connectors.

Don DeGroot of CNN Labs, designed and built a really cool test vehicle for the class. This board will be available for sale by CCN Labs in early 2013.

We looked at non-uniform and uniform lines with good and bad launches, in microstrip and stripline, as single ended and as differential. It was obvious looking at the first few measurements how strong a role the launches played above about 2 GHz. By de-embedding them low return loss measurements could be obtained up to 15 GHz, the limit to the $4 SMAs we used on the board.

One of the special exercises we did was to export the measurements from the test board as touchstone files and bring them into an analysis tool to extract the Dk and Df over frequency. All students saw that the Dk was strongly affected by the launches above about 2 GHz. This is one example where de-embedding is so important and why we focused an entire module just on how to perform fast and accurate de-embedding, and equally important, how to verify the quality of the de-embed file.

If you want to improve your VNA measurements, you really need to check out this class. Our next one is on March 1, in Longmont, CO. It will fill quickly so you’ll want to sign up early. Hope to see you there!

I’ve been teaching signal integrity for more than 20 years and keep getting asked the same questions over and over again. That’s one reason I wrote my text book, Signal and Power Integrity- Simplified.

I read so many on-line forums where engineers- both novices and very experienced, ask some very important fundamental questions, and the responders struggle or muddle through the answers.

I tried to include the answers to many of these questions in my book. Here is a short list of 20 questions which are answered in detail in my text book. If you puzzle over some of these signal integrity questions, you might find it instructive to browse through my text book.

1. Why are signal integrity problems only going to get worse as we progress on Moore’s Law? (section 1.7)
2. Why is the bandwidth of a signal related to 0.35/RT? (section 2.10)
3. What is the origin of the rule of thumb that the bandwidth of a clock signal is roughly the 5th harmonic of the clock frequency? What are the underlying assumptions? (section 2.13)
4. What is the difference between a “real” component and an “ideal” circuit element and why is this distinction important? (section 3.3)
5. What is sheet resistance and why is this an incredibly useful figure of merit? (section 4.5)
6. Why is the capacitance of a simple, short wire hanging in space about 2 pF? (section 5.2)
7. What really is inductance and how is it influenced by physical design? (section 6.3)
8. What is ground bounce and how can I reduce it? (section 6.7)
9. Why does current in a conductor re-distribute at high frequency? (section 6.16)
10. What does characteristic impedance really mean? (section 7.9)
11. How does return current really flow in a transmission line? (section 7.13)
12. How does return current flow from one plane to another when the signal transitions through a via? (section 7.14)
13. Why are there reflections? (section 8.2)
14. Do corners cause reflections and when should I care? (section 8.16)
15. Where does dissipation factor and dielectric loss come from? (section 9.6)
16. Why are the capacitance matrix elements sometimes negative? (section 10.6)
17. What is differential impedance and how is it different from odd mode impedance? (section 11.7)
18. Why is there no far end cross talk in stripline? (section 11.11)
19. Why are there always ripples in return loss and sometimes in insertion loss? (12.11)
20. What is spreading inductance and why is this important? (section 13.14)

“Most of the designs I get pulled into are really design rescues,” Jim Herrmann, Managing Partner & Principal Engineer at AppliedLogix, LLC, said at the 2012 IEEE EMC Global EMC and SI University.

From more than 25 years of hands on, practical design experience, Jim had an epiphany moment that the problems in all the designs he’s rescued have had four key root causes. He says, if you pay attention to these four key design concepts, you will avoid most of the signal integrity design problems in your next design.

Concept #1: Treat all interconnects as transmission lines and worry about their return paths as much as the signal paths. Always pay attention to the signal’s return path.

Concept #2: Try to engineer the transmission lines to look as close to a coax as possible, with the return path symmetrical around the signal path. Route in stripline, keep signals away form he edge of the board.

Concept #3: Forget the word “ground”. Board ground is just another piece of copper. Think “return path” and do everything possible to reduce the inductance of the return path.

Concept #4: Do everything possible to reduce the loop inductance of every element in the PDN. Drive out inductance in the PDN path.

Not a bad, concise list of important design guidelines to follow.

At the IEEE EMC Global EMC and SI University, Rick Hartley, a 47 year veteran of the circuit board design, SI and EMC industry, presented a short, personal account of a few of the more interesting problem boards he’s worked on over the years.

He offered a few gems of insight along the way.

“Its much easier to design a board that works the first time, and much harder to find a problem and fix it. Anything you do to fix a board after the fact is really just a band aid.”

“To control noise and EMI, we need to control containment of the electric and magnetic fields.”

He echoed the theme of the Global University: “Return paths are not just important, they are everything.”

When asked the difference between an SI problem and an EMC problem, he said, “An SI problem is when you step on your own toes. An EMC problem is when you step on someone else’s toes.”

Rick offered four examples of boards with problems, and the fixes which turned a crisis into a success.

Example #1: In a four layer board, low density board, the surface microstrip traces were referenced to a 5v plane, but no low impedance path was provided for the return current to get back to the 0v plane, connected to the driver.  He re-routed the adjacent plane to be the 0v plane, and EMI problem went away. Moral of the story: follow the return paths.

Example #2: In a high speed, multi layer board, the I/O section was carefully designed to minimize any common currents which could get out on the many 100 Mbps cables. As all the I/O were differential, the ground plane along the edge of the board was isolated from the board and only differential signals were allowed to cross the gap. But the board still radiated from the cables.

Then he noticed there were dozens of LED control lines that crossed the gap to light up the connectors. Even though they were “low speed”, they had just as fast an edge as the data. After adding low pass filters to the LED control lines, problem was eliminated. Moral of the story: “just because you think a line is low speed, doesn’t mean it is.

Example #3: “The best example of a the worst design.” The control board, with two processors and two memory banks was an 18 layer board. Many of the signal layers were filled with serpentines to keep the length skew between all the control to memory connections within 50 mils, even though the clock was 133 MHz.  To keep costs down, the 18 layer board had 4 signal layers between planes- difficult to control impedance and very high cross talk.

When he evaluated the timing, his team agreed that 300 psec was the timing skew they needed, which was a length skew of about +/- 1 inch. With this skew, the board routing could be reduced to only 10 layers, with two signals between planes, a more robust design. Moral of the story: overly tight constraints may increase the complexity of the board and introduce new problems.

Example #4: Taken from Lee Ritchey’s book, showed a 6 layer board, with large spacing between the power and ground planes, failing an EMC test. After copper fill was added to the signal layers, the board passed the radiated emissions test.

They say an expert is someone who has made all the mistakes possible. I always learn something listening to an expert. This is partly why this Global U is so valuable.

Every now and then, as I walk the floor of a trade show, a product or booth really catches my attention. At this show, I was stopped in my tracks when I saw the EMI Avengers, in battle with Evil EMI. Leading the Avengers was Eriko Yamato, as Wonder Woman.

Once she got my attention, her gentle, persistent tug would not let me go until I learned about the latest product Tech-Dream added to their distribution list, EM-ISight. This is a new near field scanning tool which moves a robotic arm in 3D around the surface of a functioning board, “sniffing” the near field at frequencies from 10 kHz to 40 GHz.

Hotspots in the local electromagnetic field at any frequency can be mapped over the product surface and even superimposed over a photo of the product to identify potential high field regions.

Of course, as Eriko points out, it’s always important to not confuse the near field with the far field. Sometimes a local near field hotspot is just a local hot spot and does not contribute to radiated emissions.

But a tool like the EM-ISight will give you a new window into the currents flowing on your board. And more information is always a good thing.

The second instructor at the IEEE Global EMC and SI University was Prof Tzong-Lin Wu, of the Dept. of EE, National Taiwan Univ. He flew in from Taiwan last night on a 22 hour flight to be here in Pittsburg, and showed no signs of jet lag.

While most of his presentation was setting the foundation of transmission line theory, he also spent time talking about return paths. This is the growing theme for this Global University. In particular, he offered a pop quiz to the 50 attendees.

He provided four different routing cases and asked our group, what would be the rating of each routed case, from best case to worst case?

Of course, the two extremes are obvious. Case 1 will be best and case 2 will be the worse.  After all, it’s important for the signal to never cross a split in the return path. But what about case 3 and 4? Which is worse, and by how much worse?

Our intuition may suggest that case 4 will be much worse than case 3. If the return path sees a continuous return, there should be little radiated emissions. So, shouldn’t case 3 be much better than case 4?

To show the impact of these four cases, Prof Wu shared simulations and measurements he has his students do at National Taiwan University.

Each of these four cases were built  in simple circuit boards and the radiated emissions measured by students. Their results are shown here.

Case 2, the signal crossing the gap, shows the most radiated emissions.

Case 4, with the signal hopping over small squares of holes in the return plane, creates the next most emissions. This was sort of expected. What is really interesting is that the case 1 and 3, with a continuous return plane, are identical. This says, even though there were gaps in the return path, but outside the width of the signal line, the gaps played no role in radiated emissions. It only takes a little web of continuous return path under the signal line to control the radiated emissions.

This was a great example of the dance between theory, measurement and simulation to illustrate the importance of return paths.

“Not all EMC rules are created equal,” Bruce Archambeault, a distinguished engineer at IBM and industry icon introduced as the theme of his tutorial at the Global University.

New to this year’s Global University is a focus on signal integrity in addition to the traditional EMC topics. About 60 engineers attended the 16 different tutorials from industry experts.

In the first session was on PCB Layout for EMC Compliance. The subtitle for Bruce’s session was really, “All about inductance and return paths.”

Bruce started out challenging us to question the relative importance of some of the many design rules we use in board design. “Should decoupling capacitors be close to the chip?” Yes, he says, but this is not the most important rule to pay attention to.

Instead, he says, paying attention to return paths of signals and the inductance of each path is probably the most important design rule to follow. The loop inductance of signal-return paths influence the switching noise in all high speed systems.  He went on to illustrate this principle by describing how geometry influences loop inductance and routing traces on aboard to control and minimize loop inductance.