Eric Bogatin's Blog: What I Learned This Month

Next No Myths Allowed Webinar: Frequency Dependent Material Properties, so what?, Thurs, Feb 25, 2010, 1 pm EST. Free, but you must pre-register here.

Spring Institute of Signal Integrity Classes, April thru May 2010, San Jose, more info and online registration here.

One of my fun activities at DesignCon is getting to conduct 10-minute interviews with signal integrity stars. These are filmed by RealTime with DesignCon and posted on their website.

I did about 10 different interviews and other reporters with RealTime did another 20 or so interviews. If you missed DesignCon, or just want to see some of the new products, materials, tools and design solutions you might have missed, you’ll want to check out the posted interviews.

In particular, here are some of my favorites you’ll want to be sure to view:
Colin Warwick, Agilent, talking about their new 3D display. In addition to looking like a couple of really cool SI Dudes, we were able to see the results from a full wave EM field solver of current flow in a via field. With the LCD shutter glasses, and interleaved left-right screen being displayed on the monitor, it really did look like the vias were standing out in front of the screen. This 3D capability is embedded in Momentum and EMPro., able to show currents, fields and voltages.

 Joel Peiffer, 3M, talking about C-ply. 3M can provide thinner than 25 micron thick C-Ply laminates, sandwiched between copper planes. The dielectric is ground up Barium Titanate filled epoxy offering a Dk of 16-20. This is great for power and ground planes. The breakdown strength of the I mil core is more than 100 v. While Joel said these materials are in production and he has customers shipping their product with C-Ply, I could not get him to reveal any customer names. He just hinted that the early adopters are cell phone manufactures, and 10-15% of all cell phones are shipped with C-Ply.

Don DeGroot, CCN-I, talking about pcb materials measurements in his company. Don came from NIST, where he worked for 12 years as a researcher in the rf test group. He’s spun his experience in precision measurements into a company that performs contract materials measurements. He talked about the transitioning of NIST engineering techniques into a commercial business and how he does practical materials characterization.

Todd Westerhoff, SiSoft, talking about what’s new from SiSoft. At DesignCon 2010, SiSoft engineers gave 3 papers. One was on “When Shorter isn’t Better.” Todd described some problems where reflections in short tracks can cause problems, especially with resonances at specific lengths. If the traces are long enough some of these resonances may damp out and not be a problem. The danger, he says, in applying design rules is you may miss these length specific problems. This is why he advocates doing a post layout analysis.

To catch all of the RealTime interviews, check out their web site.

DesignCon 2010 is right around the corner. It will be a busy time for all. As you set your schedule for the fours days of the show, be sure to add these events to your list:

Visit beTheSignal.com at booth #319. You’ll want to pick up a mug, an Appendix A -pocket guide to signal integrity design guidelines and, of course, some chocolate! Stop by and meet Susan and Laura. And I may have copies of my science fiction book, Shadow Engineer, on sale.

Monday, Feb 1, in the Theatre, I will present a 3 hour education forum, “Practical Magic: Signal Integrity Problems Disappear with the Right Tools“. My Agilent buddies and I will be showing about a dozen demos of some really cool hardware and software tools that I think should be in every signal integrity engineer’s tool box. check out my youtube video!

Tues, 8:30 am, I will present a paper “Frequency Dependent Material Properties: So What?”, with Don DeGroot, Sanjeev Gupta and Colin Warwick. If you are wondering about all the hype associated with “causal material properties” and want to know how does this apply to me, you’ll want to check out this talk.

Tues, 9:20, my colleague, Paul Huray, will present, “Impact of Copper Surface Texture on Loss, a Model that Works.” There’s a lot of buzz these days about rms roughness of copper. Come hear Prof Huray explain it’s really the surface texture of the copper, not just the rms roughness, that affects the extra losses from rough copper. You may find, as I discovered, that “everything you know about current and signal propagation is wrong.” Come hear the right way of thinking about how signals really propagate on interconnects.

Tues, 3:45 pm, I will participate on a panel discussion, “Science Fiction…is it really fiction?” This has got to be one of the more fun events at DesignCon, at least for me. I get to share the panelist table with Gentry Lee, famed co-author with Aurthur C. Clark of the Rama series, among other books, and noted scientist at JPL. We will talk a little about our visions of the future and open up the floor to discussion. Rumor has it, some of us might have books available for a book signing!

Wed 8:30 am. If you missed my education forum on Monday afternoon, you can catch it again on Wed morning.

I’m exhausted already, just writing about the exciting happenings at DesignCon 2010. See you there!

I recently had a chance to don a pair of LCD shutter glasses and stare into a synthesized 3D image that popped out of the screen at me. Cascading colors flowed around obstacles. I could move my head around and see how the pattern of colors moved in and around the objects in the foreground.

No, this wasn’t a scene I witnessed in Avatar, which I also viewed in 3D IMAX, it was a demo of Agilent’s new 3D glasses incorporated in an upgrade to their popular Momentum field solver suite. I had a chance to sample the new 3D vision system at the FPGA Camp in San Jose on Nov 11, 2009. Wow! Pretty darn cool!

Tightly coupled into the Agilent’s ADS simulation environment are Momentum, which does 2.5 D full wave simulations and EMPro which does 3D full wave simulation. While both of these tools can show 3D perspectives of the static or dynamic, electric or magnetic fields or currents in and around conductors, the simulations seem to come alive when viewed in true 3D.

To make this possible, Agilent has teamed with Nvidia to leverage their high end GPUs for the visual processing. The 3D images are generated by projecting on the monitor an image for just the right eye, while synchronized with the opened right eye shutter on the LCD glasses, and then projecting the image for the left eye.

The frame rate is high enough so that you don’t perceive the flicker, but see the screen in true 3D, giving the sense of having the object, and its field distribution, projecting in front of the screen. I suppose the next step is to incorporate a 3D mouse pointer and be able to move it around to interact with the 3D environment.

If you want to learn more about this novel imaging feature, be sure to check out the webinar Agilent is providing on Jan 21, 2009. You can sign up at this link.

I can’t wait to find the right demos to use for my upcoming live classes. One of these days soon, if I hand you a pair of LCD glasses when you walk into the room, you’ll know what to expect.

Next No Myths Allowed Webinar, “Selecting Capacitor Values for the PDN”, Dec 9  2009, 1 pm EDT. Signup now.

The co-evolution of finer pitch packages and higher interconnect density circuit boards has enabled the explosion of mobile products for the consumer market, but is wrecking havoc in the test world.

More than 15 years ago, portable, consumer electronic products such as the hand held camcorder, drove the introduction of fine pitch packages, which have become known as chip scale packages (CSP). With pitches less than 20 mils (0.5 mm) and pad densities much higher than 100/square inch, conventional circuit board technology could not provide the cost effective, high density interconnect for this new generation of mobile product.

Higher density circuit board technology co-evolved along with CSPs. Multi layer build up or high density interconnect (HDI) or micro via substrates all use finer lines and smaller vias than traditional, mechanically drilled circuit boards. Every single cell phone manufactured today uses CSPs and microvia substrates.

While consumer products are well suited to leverage an interconnect form factor of finer pitch CSPs and higher interconnect substrates, the tester environment is not.

From the pin electronics of the tester to the pads on the chip being tested is a complex, Rube Goldberg hierarchy of interconnects. This system is designed to provide high performance electrical connections between thousands of pads on the pin electronics chips to thousands of pads on the die or wafer, and the flexibility of re-using most of the interconnects for thousands of different chip designs and millions of individual parts tested, while still allowing the pin electronics to be field upgradable.

The interface between the tester and the device to be tested is the load board. This is a massive space transformer circuit board. Pads on the bottom surface on 50-100 mil centers touch compliant pins connected to the tester electronics cabling or circuit boards. With more than 10,000 pins, even a 50 gm contact force per pin needs more than 1,000 pounds of force between the load board and the tester. It must be mechanically rigid which is why they are so thick. Typical thickness specs for load boards range from 150 to 200 mils.

To accommodate the more than 10,000 connections to the pin electronics, load boards have to be large, typically more than 15 inches on a side.

The electrical specifications for the load boards have to be higher performance than product boards. It’s not enough that the device works on the load board, the load board must have minimal impact on the signal quality of the device being tested so its intrinsic performance can be evaluated.

This translates to wider traces in controlled impedance with thicker dielectric layers. The long traces will often require more expensive, low loss dielectrics and multiple, solid, power and ground planes. These high performance interconnects are implemented with 16-30 layers of alternating signal layers and power and ground planes.

Load boards are driven by a different set of forces than product boards. They have to be large area, thick, many layers and use high performance, read more expensive, laminate materials.

On the top side of the load board are the connections to the device to be tested. Since the package already provides the space transformer from the die pad pitch to the circuit board pad pitch, historically, just a one to one compliant socket has been needed to interface the package under test to the load board.

As chip scale packages migrate to finer pitch, HDI substrate technology co-evolves to provide the higher interconnect needs. But the load board, with its large area, thick substrate and many layers cannot keep up. Here lies the challenge. How do you fabricate a load board, 200 mils thick, 18 inches on a side with 26 layers and have pads on the surface that can interface to a socket on 0.4 mm centers? And CSPs are migrating to even finer pitch.

While integrating a few HDI layers on top of a conventional load board to do the geometry transformation is being done, it is very expensive in direct cost and in yielded cost.

An alternative solution is to adopt the approach for testing a single die or whole wafer: add a space transformer from the fine pitch pads of the device to the coarse pitch pads of the circuit board.

After all, needle probe cards have been doing this for more than 40 years. Other technologies have evolved for wafer probing that use a ceramic substrate as the space transformer. In the Form Factor probe cards, for example, MEMs compliant tips are fabricated on the top of the ceramic substrate on pitches as fine as 2 mils. The pads on the bottom of the ceramic substrate interface to the load board with another compliant one to one interposer but on pitches of 50 to 100 mils.

This same approach can be implemented for final test of packaged devices. A daughter board acts as the space transformer from the finer pads pitch of the CSP to the coarser pad pitch of the load board.  A fine pitch socket technology is used on the top surface and a board to board interposer is used between the daughter card and the conventional load board.

An example of such an architecture, from R&D Circuits, is shown to the left.

Jim Russell, president of R&D Circuits says the cross over where this approach is lower cost than conventional load boards is for devices with 0.4 mm pitch and below. He goes on to say, “this architecture also allows the same, high value load board, to be used with multiple devices in a related family by just changing out the daughter card.”

In July 2008, R&D Circuit acquired Anestel Corporation which developed a board to board interposer based on patterned Kapton films with columns of silver filled silicone rubber. When compressed between two boards, this film is a one to one interposer. The typical connection pitch is 0.8 mm.

The daughter boards act as the space transformers. Being small size, few layers and high performance, they can ride the HDI wave and evolve with the finer pitch chip scale packages. They shield the load board from technology advances of the package devices, allowing the load board to be optimized for the tester environment.

Our thirst for higher performance, lower cost mobile consumer products will absolutely drive smaller, higher pad density devices, with a form factor indistinguishable from the chip. For load boards to keep up in final test it’s not surprising that the daughter card architecture currently used in wafer sort, should be adopted for package test.

see you in cyberspace!

Mark your calendars for our next No Myths Allowed webinar, scheduled for Wed, May 6, 2009 at 1 pm EDT. Like all of our webinars in this series, it will last about 45 minutes with 15 minutes for Q&A and be well worth your time.

This one is entitled, “S-Parameters, Signal Integrity and You.” In 45 minutes, we will introduce the most important features of S-parameters, starting at the very beginning and exploring some of their features and why they are becoming the defacto standard to describe the high frequency behavior of interconnects.

I’ve started a list of the questions we will address in our brief 45 minutes. If you have another question important to you not on the list, drop me a note and I will consider adding it to the webinar. Here is what we will cover:

• What are S-parameters?
• Why should I care?
• Where do they come from?
• How are they simulated?
• How are they measured?
• How accurate are they?
• How do I look at them?
• What’s the deal with differential S-parameters?
• How do I measure differential S-parameters?
• What can I learn about an interconnect from them?
• What can I do with them?
• What are some of the common pitfalls I should watch out for?
• What are some of the resources I can leverage to get more value from S-parameters?

You must sign up by May 4th, in order to attend. We will send out an email note with the access information the day before the webinar. The webinar will be recorded and posted to our website, along with all our other video recordings, and available to all paid subscribers the day after the presentation.

Hope to see you in cyberspace!

Our next No Myths Allowed webinar, May 6, 1 pm EDT, “S-Parameters, Signal Integrity and You”. Details and registration available at www.beTheSignal.com

Fiber weave induced skew in high speed serial links is a serious problem at 5 Gbps and above, but a new option from Dielectric Solutions may dramatically reduce this problem. Their solution, NovaSpeed 1080,  is a new low Dk glass fiber woven into a flatter fabric.

At IPC Expo last week, I had a chance to chat with John Kuhn, VP of Technology at Dielectric Solutions. You can watch my interview with him which I did for Real Time with IPC. This is a topic I’ve written on a number of times in the past. Here’s what I learned from John.

Glass weave induced skew arises when signals in the two lines that make up a differential pair travel at different speeds due to local variations in the dielectric constant they see. The dielectric constant variation is due to the higher dielectric constant of the glass weave, typically 6-7, compared to the resin, typically 3-3.5, and its bunching into fiber bundles. This is illustrated in the figure above.

If one line in a pair happens to be closer to a fiber bundle than its partner line, it will see a higher dielectric constant and travel slower than its partner. By the time the two signals come out the end of equal length lines, the slow path will be delayed compared to the faster path and there will be time delay skew between them.

This skew causes an asymmetry between the signals in the two lines and converts some of the differential signal into common signal, distorting the rise time of the differential signal, causing ISI, collapse of the eye and deterministic jitter.

In FR4 systems the typical glass weave skew varies depending on the weave pitch, the line to line pitch and the glass weave. While it may run to a worse case of 10 psec/inch, it may typically be 2-4 psec/inch. By its nature, the effect of glass weave skew is statistical.

The spec for the worst case acceptable skew is usually about 10% of a unit interval. At 5 Gbps, in PCIe Gen II, for example, the unit interval is 200 psec and the maximum acceptable total skew is less than 20 psec. This means that it is easily possible for the two lines that make up a differential pair to violate a skew spec after running only 5 inches or less.

It doesn’t mean no pairs will work longer than 5 inches. Weave induce skew is a statistical problem and depends on the random alignment of the signal track precisely over the worst case of the glass weave tracks. But, if you build enough boards with enough lines, some of them are bound to show excessive skew, and show a high bit error rate.

Fiber skew is one of the hardest problems to debug. Its signature is poor eye opening in one channel while an adjacent channel is just fine. Or, all the paddles cards in a collection might work but not in all combinations with a specific backplane. If you see these problems, suspect fiber weave induced skew as the root cause.

While there are a number of design based solution, a new technology solution is available that should be added to your tool box. Dielectric Solutions has introduced a new type of glass fabric which dramatically reduces the fiber weave skew effect. Their solution comes from two innovations.

They formulate their own glass, melt it down, extrude it into glass fiber and weave the fiber in a fabric. This gives them complete control over the entire glass fabric process. They’ve formulated a new low Dk glass with a dielectric constant of about 4.5, compared to the standard E glass with a dielectric constant of 6.8.

Second, they weave this fiber into a flat fabric so there is little lateral variation in the glass density. This combination means significant reduction in the glass weave skew. While FR4 and E glass combinations might show a maximum skew of 10 psec/inch, the worst case skew with the low Dk spread glass fabric is less than 1.6 psec/inch. This means much more margin in current systems, and enabling higher bandwidth systems when fiber skew sets the limit.

In the quest for higher bit rates and longer runs, the NovaSpeed fabric from Dielectric Solutions is an exciting alternative that can dramatically improve performance. One less problem for the high speed signal integrity engineer to worry about.

Hope to see you in Cyberspace at our next webinar!

This month, I published a paper in PCD&F titled “Don’t let your vias stub their toes“, about how the residual via stub in a thick board, like a backplane, can cause hugh problems in high speed serial links. One way to tame this problem is to backdrill the via stub. In fact, all high speed serial link backplanes use backdrilled vias.

I got a note from Tom Paur of PerfecTest, who told me about a small hand tool they created to test the drill depth of back drilled vias. Here’s an example of it:

Preset, precision pins are inserted into the backdrilled hole and a light idenicates the pass-fail for the drilled hole depth. As backdrilling becomes more common, this is a handy, quick test for the quality of the drill depth without having to cross section the board.