Eric Bogatin's Blog: What I Learned This Month

Getting started in signal integrity? check out the pdf copy of Chapter 1 from Signal and Power Integrity- Simplified, available for free download on www.beTheSignal.com

Today, signal integrity has become the limiting factor in all products operating at 200 MHz and above. This includes all communications products, servers, personal computer and even cell phones. Not paying attention to signal integrity in the beginning of a design means the product may not work at bring-up.

While the highest end applications- telecommunications, test and measurement, super computers, mainframes and servers have been in this regime for more than thirty years, mainstream consumer products have been sensitive to signal integrity effects for only about ten years.

At the dawn of the “mainstream signal integrity” era, before “social networking” was even imagined, there was the SI-List. Almost all signal integrity engineers, at one time in their career, have participated on this email distribution list, either posting questions, answering questions, participating in the debates or listening to the chatter.

Sixteen years ago, on May 16, 1994, the SI-List was born with 30 members on the charter email list.

Ray Anderson, then a recent convert to signal integrity from years as a microwave engineer, came up with the idea of an email discussion group to continue the question and answer period from the last day of a four day short course he had taken on signal integrity.

He had recently joined Sun Microsystems as a signal integrity engineer. His jump start into this new field was “Electrical Modeling, Simulation and Design of Electronic Packages”, taught by Raj Mittra, Paul Franzon and Jose Schutt-Aine in San Jose, CA on May 9-12, 1994.

“On the last day of class I said it would be really neat if we put together a mail list to pose questions and answers to continue the discussions. I went back to my office on Monday and hacked together an email list on the SPARC2 worskstation sitting in my office at Sun Microsystems with the thirty names from the class.”

Figure 1. Ray Anderson in his package characterization lab at Xilinx, where he is currently a senior engineer.

Sixteen years later, there are 4,000 members on the SI-list spread over more than 34 countries. The range of participants starts with novices and students in college and extends to world renown experts such as Scott McMorrow, Steve Weir, Istvan Novak and Todd Hubbing.

“The typical questions posed to the list today, are not that different from the early days,” Ray says. “Over the 18 years I’ve been in signal integrity, the technology has changed, but the physics hasn’t.”

The questions posed on the SI-list are an indication of the most confusing or controversial topics in signal integrity. Power distribution design (PDN) has always been a hot topic. How many and what value decoupling capacitors do I need on my board and where should they be placed are the most common questions asked, followed by what is the inductance of a via?

Questions range from general, open ended topics, such as which is better a VNA or TDR? to specific design questions about the timing delay between data and clock in the DDR3 JEDEC timing spec.

The hot topic these days include the frequency dependence of the dielectric properties of laminates and the use of S-parameters to describe interconnect performance including causality and passivity.

“When I started the list and saw it grow so fast, I had visions of herding cats. But, it has turned out to be remarkably well self managed. Peer pressure usually establishes the norms for behavior,” Ray says.

In addition to questions and technical discussion, it is also a bulletin board for announcements about upcoming webinar, seminars, short courses or job announcements. List etiquette discourages recruiters from posting job openings in the SI field, except by the hiring manager directly.

There are always those who abuse the list. However, over the 16 years of its existence, there have only been 12 individuals banned from the list. One of the biggest frustrations with long time participants of the list is with the same, fundamental questions being asked by “newbies.”

“If you are going to ask a question,” Ray advises, “do your homework first. Make an attempt to solve the problem yourself. Read some books, search the web and the list archives, then pose the questions. Don’t just try to get someone to do your work for you.”

To subscribe to the SI-List, go to : http://www.freelists.org/webpage/si-list

To view the archives of postings, go to: http://www.freelists.org/archive/si-list/

Next No Myths Allowed Webinar: Frequency Dependent Material Properties, so what?, Thurs, Feb 25, 2010, 1 pm EST. Free, but you must pre-register here.

Spring Institute of Signal Integrity Classes, April thru May 2010, San Jose, more info and online registration here.

One of my fun activities at DesignCon is getting to conduct 10-minute interviews with signal integrity stars. These are filmed by RealTime with DesignCon and posted on their website.

I did about 10 different interviews and other reporters with RealTime did another 20 or so interviews. If you missed DesignCon, or just want to see some of the new products, materials, tools and design solutions you might have missed, you’ll want to check out the posted interviews.

In particular, here are some of my favorites you’ll want to be sure to view:
Colin Warwick, Agilent, talking about their new 3D display. In addition to looking like a couple of really cool SI Dudes, we were able to see the results from a full wave EM field solver of current flow in a via field. With the LCD shutter glasses, and interleaved left-right screen being displayed on the monitor, it really did look like the vias were standing out in front of the screen. This 3D capability is embedded in Momentum and EMPro., able to show currents, fields and voltages.

 Joel Peiffer, 3M, talking about C-ply. 3M can provide thinner than 25 micron thick C-Ply laminates, sandwiched between copper planes. The dielectric is ground up Barium Titanate filled epoxy offering a Dk of 16-20. This is great for power and ground planes. The breakdown strength of the I mil core is more than 100 v. While Joel said these materials are in production and he has customers shipping their product with C-Ply, I could not get him to reveal any customer names. He just hinted that the early adopters are cell phone manufactures, and 10-15% of all cell phones are shipped with C-Ply.

Don DeGroot, CCN-I, talking about pcb materials measurements in his company. Don came from NIST, where he worked for 12 years as a researcher in the rf test group. He’s spun his experience in precision measurements into a company that performs contract materials measurements. He talked about the transitioning of NIST engineering techniques into a commercial business and how he does practical materials characterization.

Todd Westerhoff, SiSoft, talking about what’s new from SiSoft. At DesignCon 2010, SiSoft engineers gave 3 papers. One was on “When Shorter isn’t Better.” Todd described some problems where reflections in short tracks can cause problems, especially with resonances at specific lengths. If the traces are long enough some of these resonances may damp out and not be a problem. The danger, he says, in applying design rules is you may miss these length specific problems. This is why he advocates doing a post layout analysis.

To catch all of the RealTime interviews, check out their web site.

DesignCon 2010 is right around the corner. It will be a busy time for all. As you set your schedule for the fours days of the show, be sure to add these events to your list:

Visit beTheSignal.com at booth #319. You’ll want to pick up a mug, an Appendix A -pocket guide to signal integrity design guidelines and, of course, some chocolate! Stop by and meet Susan and Laura. And I may have copies of my science fiction book, Shadow Engineer, on sale.

Monday, Feb 1, in the Theatre, I will present a 3 hour education forum, “Practical Magic: Signal Integrity Problems Disappear with the Right Tools“. My Agilent buddies and I will be showing about a dozen demos of some really cool hardware and software tools that I think should be in every signal integrity engineer’s tool box. check out my youtube video!

Tues, 8:30 am, I will present a paper “Frequency Dependent Material Properties: So What?”, with Don DeGroot, Sanjeev Gupta and Colin Warwick. If you are wondering about all the hype associated with “causal material properties” and want to know how does this apply to me, you’ll want to check out this talk.

Tues, 9:20, my colleague, Paul Huray, will present, “Impact of Copper Surface Texture on Loss, a Model that Works.” There’s a lot of buzz these days about rms roughness of copper. Come hear Prof Huray explain it’s really the surface texture of the copper, not just the rms roughness, that affects the extra losses from rough copper. You may find, as I discovered, that “everything you know about current and signal propagation is wrong.” Come hear the right way of thinking about how signals really propagate on interconnects.

Tues, 3:45 pm, I will participate on a panel discussion, “Science Fiction…is it really fiction?” This has got to be one of the more fun events at DesignCon, at least for me. I get to share the panelist table with Gentry Lee, famed co-author with Aurthur C. Clark of the Rama series, among other books, and noted scientist at JPL. We will talk a little about our visions of the future and open up the floor to discussion. Rumor has it, some of us might have books available for a book signing!

Wed 8:30 am. If you missed my education forum on Monday afternoon, you can catch it again on Wed morning.

I’m exhausted already, just writing about the exciting happenings at DesignCon 2010. See you there!

In addition to social networking, the web has enabled and revolutionized open sourced activities.

Linux started its life as an open source operating system, and has evolved into dozens of variations like Ubuntu. Wikipedia is now a top rated, open source information reference. Even astronomy and astrophysics research has entered the open sourced arena with the Galaxy Zoo project.

As an example of “online introspection,” Wikipedia states, “A main principle and practice of open source software development is peer production by bartering and collaboration, with the end-product (and source-material) available at no cost to the public.”

This is exactly the principle behind the FPGA Camp, an example of an open source conference. Vikash Rungta, a principle organizer, offered his motivation for the conference: “I love FPGAs and I wanted to get other FPGA people together to talk about FPGAs.” FPGAs, of course, stands for Field Programmable Gate Arrays.

Vikash has worked with FPGAs for more than 12 years, at start ups, at Cisco and now most recently at Infinera Corp. He sees FPGAs as sometimes an orphan topic at conferences like DAC and IEEE programs.  He wanted to attend a conference that focused just on FPGAs. When he couldn’t find one, he started one of his own.

His idea is to have an evening gathering once a quarter, free to all attendees, with highly rated speakers, food and refreshments and lots of opportunity to mingle, network and talk shop with other FPGA designers.

Amolok Badesha, an application engineer with Agilent Technologies, was one of the organizers of the first event, held on Aug 26, 2009. He and Vikash put the whole evening program together in less than two weeks just talking to friends. They arranged a room at Juniper Networks, asked a few vendors to pay for food and invited six experts to speak.

Salman Jiva of Altera, Steve Weir of Teraspeed and Marty Jain from Lattice were some of the speakers at the first event. This “Camp” focused on High Speed Serial Interfaces: Protocols, IPs and Devices. Once word got out to the design community, the free conference was quickly booked to capacity with 140 engineers.

The next event was held on Nov 11, 2009 at the Agilent Technologies auditorium. A dozen vendors had table-top booths and more than 150 engineers attended. I was one of the speakers and talked about “How the board will screw up your beautiful transceiver signals, and what you can do about it.”

A copy of the handouts of my talk can be downloaded from beTheSignal.com, and subscribers can view a recording of my lecture. You can catch an interview I gave Vikash which is posted on the FPGA Camp web site and on Youtube.

Vikash’s plan is to conduct these open source, low overhead, free conferences once a quarter. The organizers are all volunteers, the facilities are donated, the speakers do it for the opportunity to share and the vendors pay for the food and refreshments.

Where does the energy come from that drives these sorts of open source events? As Vikash says, “I do it for the passion. I love all things about FPGAs.” He sounds like an FPGA evangelist.

Next No Myths Allowed Webinar, “Selecting Capacitor Values for the PDN”, Dec 9  2009, 1 pm EDT. Signup now.

“There ain’t no such thing as a free lunch,” is how the phase, popularized in Robert Heinlein’s book, The Moon as a Harsh Mistress, usually goes.

But that’s not how Scott McMorrow, director of engineering at Teraspeed, uses the phrase. He is fond of saying “There ain’t no such thing as a free launch.”

It’s sort of ironic, because he and his team are world experts at providing nearly free launches.

A launch is a transition from one transmission line geometry to another. While a coax cable and a stripline in a circuit board may each be electrically transparent, when one transitions into the other, the interface, or launch, will always show up as a discontinuity.

This discontinuity will cause a reflected signal and a reduction in the transmitted signal, which shows up in the insertion loss. The larger the discontinuity, the bigger the impact on the insertion loss. And, due to the physical size of a launch, it is always more of a problem at higher frequencies.

To minimize the launch discontinuity, Teraspeed recommends using a surface mount SMA connector and carefully optimizing the features of the launch via pad stack.

The figure to the left shows the TDR response of a conventional, well designed launch and a Teraspeed “free launch”, with a roughly 35 psec rise time signal and 5 Ohms per division. This was reported, most recently, at DesignCon 2009 and can be found in the reprinted article on the Simberian web site.

The pad stack includes the capture pads, the via barrel diameter, location of return vias, and clearance holes in any planes. Of course, what works in one board will be not always be the best design in another board due to the precise combination of signal layer and plane layer assignments and dielectric thicknesses.

Translating a specific board’s pad stack into the virtual world of a 3D field solver enables you to quickly optimize the clearance holes for a transparent launch. For example, if the launch impedance is high, make the clearance holes smaller. If the impedance is low, make the clearance holes larger.

This principle of a “free launch” applies to all transitions, especially important from the planar geometry of a circuit board to the 3D geometry of a connector.

Samtec made popular the term, “the final inch” to describe the break out region (BOR) of a circuit board connector’s via field. Using this principle of optimizing a few features in the immediate region of the launch, they can make the circuit board transitions into their connectors nearly transparent.

When done well, the transition from any connector to board traces can be transparent. This is important when designing test vehicles, ATE load boards and high performance product boards. As PCIe and USB enter the 5 Gbps and above regime, designing transparent launches will be an important skill.

For information on this and other multi gigabit topics, check out our new class, Multi Giga Bit Design (MGBD).

Hope to see you in cyber space at our next webinar!

Check out our next public classes: Essential Principles of Signal Integrity and Advanced Signal Integrity Design, Oct 11-14 in Hillsboro, OR.

Check out our next No Myths Allowed Webinar, “Link Analysis with Return Path Discontinuities”, presented free on July 7, 1 pm EDT.

“Ten orders of magnitude in productivity gains in half a century,” is how Tom Di Stefano, one of the founders of Tessera, started out his keynote address to the International Wafer Level Packaging Conference, Oct 15, 2008. If you missed his talk, you can read the transcript.

The consumer products we enjoy today are all based on riding Moore’s Law, which is really driven by the integration made possible by photolithography and processing whole wafers of chips.

Tom argues that historically, packaging technology has not really contributed much to this cost-performance curve. It’s been dominated by mechanical processing: stamping lead frames, singulation of chips and individual processing. That is, until the introduction of Wafer Level Packaging (WLP) in the last 15 years.

WLP has the potential of applying the integration advantages of IC processing to packaging, enabling chip scale packages that can ride the cost-performance curve that silicon chips have enjoyed. If the techniques associated with the back end of chip manufacture: assembly, packaging and test, are of interest to you, you’ll want to check out the new journal, “Microconnections” available in print and on-line.

I occasionally write a column in this journal, focusing on signal integrity issues associated with packaging and test. My last column addressed the question of  the Impedance of a test pin in a socket and my next column is about S-parameters.

If you want to get involved in this field, you’ll want to check out the list of conferences coming up by clicking here and see the most complete list I’ve come across anywhere online.

Enjoy the next issue.

Mark your calendars for our next No Myths Allowed webinar, scheduled for Wed, May 6, 2009 at 1 pm EDT. Like all of our webinars in this series, it will last about 45 minutes with 15 minutes for Q&A and be well worth your time.

This one is entitled, “S-Parameters, Signal Integrity and You.” In 45 minutes, we will introduce the most important features of S-parameters, starting at the very beginning and exploring some of their features and why they are becoming the defacto standard to describe the high frequency behavior of interconnects.

I’ve started a list of the questions we will address in our brief 45 minutes. If you have another question important to you not on the list, drop me a note and I will consider adding it to the webinar. Here is what we will cover:

• What are S-parameters?
• Why should I care?
• Where do they come from?
• How are they simulated?
• How are they measured?
• How accurate are they?
• How do I look at them?
• What’s the deal with differential S-parameters?
• How do I measure differential S-parameters?
• What can I learn about an interconnect from them?
• What can I do with them?
• What are some of the common pitfalls I should watch out for?
• What are some of the resources I can leverage to get more value from S-parameters?

You must sign up by May 4th, in order to attend. We will send out an email note with the access information the day before the webinar. The webinar will be recorded and posted to our website, along with all our other video recordings, and available to all paid subscribers the day after the presentation.

Hope to see you in cyberspace!

At DesignCon 2008, I ran into Don DeGroot who has started up a new company to perform high bandwidth and high quality measurements using TDR and VNA instruments. I just got a note from him that he has opened up a new web site and has his shingle officially out.

He has a TDR and VNA and analysis software tools and can perform high bandwidth measurements for you, or show you how to do your own measurements. The work he does nicely compliements the content of our Signal Integrity Characterization Techniques class, which we are offering in San Jose on Aug 12-13. If you are looking for measurement services, check out his web site.