Published by Eric Bogatin on 10 Oct 2009
10/10/09 TANSTAAFL
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“There ain’t no such thing as a free lunch,” is how the phase, popularized in Robert Heinlein’s book, The Moon as a Harsh Mistress, usually goes.
But that’s not how Scott McMorrow, director of engineering at Teraspeed, uses the phrase. He is fond of saying “There ain’t no such thing as a free launch.”
It’s sort of ironic, because he and his team are world experts at providing nearly free launches.
A launch is a transition from one transmission line geometry to another. While a coax cable and a stripline in a circuit board may each be electrically transparent, when one transitions into the other, the interface, or launch, will always show up as a discontinuity.
This discontinuity will cause a reflected signal and a reduction in the transmitted signal, which shows up in the insertion loss. The larger the discontinuity, the bigger the impact on the insertion loss. And, due to the physical size of a launch, it is always more of a problem at higher frequencies.
To minimize the launch discontinuity, Teraspeed recommends using a surface mount SMA connector and carefully optimizing the features of the launch via pad stack.
The figure to the left shows the TDR response of a conventional, well designed launch and a Teraspeed “free launch”, with a roughly 35 psec rise time signal and 5 Ohms per division. This was reported, most recently, at DesignCon 2009 and can be found in the reprinted article on the Simberian web site.
The pad stack includes the capture pads, the via barrel diameter, location of return vias, and clearance holes in any planes. Of course, what works in one board will be not always be the best design in another board due to the precise combination of signal layer and plane layer assignments and dielectric thicknesses.
Translating a specific board’s pad stack into the virtual world of a 3D field solver enables you to quickly optimize the clearance holes for a transparent launch. For example, if the launch impedance is high, make the clearance holes smaller. If the impedance is low, make the clearance holes larger.
This principle of a “free launch” applies to all transitions, especially important from the planar geometry of a circuit board to the 3D geometry of a connector.
Samtec made popular the term, “the final inch” to describe the break out region (BOR) of a circuit board connector’s via field. Using this principle of optimizing a few features in the immediate region of the launch, they can make the circuit board transitions into their connectors nearly transparent.
When done well, the transition from any connector to board traces can be transparent. This is important when designing test vehicles, ATE load boards and high performance product boards. As PCIe and USB enter the 5 Gbps and above regime, designing transparent launches will be an important skill.
For information on this and other multi gigabit topics, check out our new class, Multi Giga Bit Design (MGBD).
Hope to see you in cyber space at our next webinar!
Steve did a super analysis and sent me the plot to the left which shows what is going on. In his example of two coupled microstrips, the line widths were 300 microns, which is 12 mils. The dielectric thickness he used was 254 microns, or 10 mils. This comes out as a relatively high impedance line, about 70 Ohms, single-ended.
In all the lectures I give on differential pairs and differential pair design, I always say that you should forget the words “differential mode” or “common mode.” Using these terms confuses the use of the words and, I think, significantly confuse our intuition and make it even harder to understand this already confusing topic.
OK, so I have given up on my unwinnable quest to change the industry, but I still think if you want to calibrate your intuition and really understand what goes on when a differential or common signal propagates down a differential pair and it sees a differential impedance or a common impedance, don’t use the words differential mode or common mode. It is not needed and will screw up your intuition.
In the paper, “Relationship Between Connector Contact Points and Common-mode Current on a Coaxial Transmission Line,” by Hayahi, Mizuki and Sone, of the Tohoko University in Sendai, Japan, the authors illustrate this principle with a simple construction.
In the paper, “Effectiveness of Shield Termination Techniques Tested with a TEM Cell and Bulk Current Injection,” by Bradley and Hare of NASA Langley Research Center in Hampton, VA, the authors show by direct measurement the radiated emissions from cable assemblies with different shield termination schemes.
At 28%, the consensus was S11, followed by SDD11 at 23%. This is surprising, as neither answer is correct. This topic is covered in detail in the
cavity can be very large and long range.
When Thiokol was designing the diameter of the solid fuel booster, so the legend goes, they had to limit its OD based on fitting on a railroad car, which is limited by the axle pitch, which is limited by a pair of horses asses.
Many connector companies, such as
Motes, small,
Like all of our webinars in this series, it will last about 45 minutes with 15 minutes for Q&A and be well worth your time.
is “it depends”, it’s not always the best answer. In the case of transparent vias, the limitation is really the via stub. The correct answer is the fourth one, minimize the stub length, which 23% of you correctly answered.