What I Learned this Month

It’s easy to measure S-parameters. It’s challenging to measure them without introducing artifacts and interpret the measurements correctly.

Our newest class, Hands on Workshop for S-Parameter Measurements (HOW-SPM), was created to teach these valuable measurement and analysis skills. We just finished our first class and it was a wonderful success.

This class was limited to only 12 students and filled up in the first 2 weeks after it was posted. Our next class on March 1, will also fill quickly.

Pairs of students shared a SPARQ, Signal Integrity Network Analyzer from Teledyne LeCroy, operating up to 40 GHz. All the principles and techniques we taught applied to ANY VNA. We limited attendance to 12 students total, so that everyone would get stick time and individual attention from our expert instructors. During the course of the day, everyone measured a variety of samples, each illustrating different measurement and analysis principles.

Resistors were used to illustrate how the measurement from a DMM at DC translated into the same resistance as obtained with a 40 GHz VNA- in the frequency and time domains.

A range of quality level 50-Ohm cables were measured to show the wide difference in bandwidth of good and bad cables, and the role of the connectors. We used port re-normalization to change the port impedances to view 75 Ohm cables and de-embedded the launches to show the impact at low frequency from the the port impedance, and the influence at high frequency from the connectors.

Don DeGroot of CNN Labs, designed and built a really cool test vehicle for the class. This board will be available for sale by CCN Labs in early 2013.

We looked at non-uniform and uniform lines with good and bad launches, in microstrip and stripline, as single ended and as differential. It was obvious looking at the first few measurements how strong a role the launches played above about 2 GHz. By de-embedding them low return loss measurements could be obtained up to 15 GHz, the limit to the $4 SMAs we used on the board.

One of the special exercises we did was to export the measurements from the test board as touchstone files and bring them into an analysis tool to extract the Dk and Df over frequency. All students saw that the Dk was strongly affected by the launches above about 2 GHz. This is one example where de-embedding is so important and why we focused an entire module just on how to perform fast and accurate de-embedding, and equally important, how to verify the quality of the de-embed file.

If you want to improve your VNA measurements, you really need to check out this class. Our next one is on March 1, in Longmont, CO. It will fill quickly so you’ll want to sign up early. Hope to see you there!

I teach two classes in which I introduce essential principle #5, that whenever the instantaneous impedance the signal sees changes, a reflected signal is created. Almost without fail, at the end of the class, some brave soul, usually a younger engineer, comes up to me and asks that very important question, “Why?”

The flip answer is that if there were no reflected signal created when the instantaneous impedance the signal encounters changes, the universe would blow up. The reflected signal is created to keep the universe in harmony.

To see the problem, look at the figure to the left. The instantaneous impedance defines the ratio of the propagating voltage to the current in each region. If the instantaneous impedance in the two regions is different, the ratio of the voltages to currents in the two regions must be different.

Think about the incident voltage that hits the interface and continues to the other side. If there were no reflections, and the incident and transmitted voltages were different, there would be an electric field between two points on either side of the interface. The closer these two points get, the larger the electric field.

If we bring the two points really, really close but still sitting in the different impedances, the field could become extremely large, and the universe could blow up.

So, maybe the voltages have to be the same. But, if the impedances are different, the ratios of the voltages to the currents in the two regions have to be different different. If the voltages are the same, the currents into the interface must be different. But, if there is more current going into the interface than transmitted out, charge will build up and if we wait long enough, the universe will explode at the interface.

These two conditions, of the voltages being continuous and the net current into the interface being 0, are called boundary conditions. They cannot both be met without a reflected signal being created. The details of how the reflected signal helps to keep the universe in harmony and the derivation of the reflection coefficient and transmission coefficient can be found in the brief article I wrote for PCD&F magazine.

So we see that the most common signal integrity problem, the creation of reflections from impedance changes and the signal distortion that results from multiple reflections, is really a good thing. Without it, the universe would blow up.

Cross talk between two single-ended or two differential channels can be a problem which causes a product to fail. While a typical required signal to noise ratio (SNR) for some systems may be as low as 20 dB, in mixed signal applications it may be as high as 60 to 80 dB and in lossy channels, it may need to be above 45 dB.

To various extents, the coupling between aggressor and victim channels depends on the signal rise time, coupled lengths, interconnect density and line impedances. But not all system simulators take into account all the couplings which can cause problems. This is why it is sometimes important to measure the channel to channel cross talk.

S-parameters provide a natural way of characterizing cross talk between channels because each term in the S-parameter matrix really describes the coupling of one port into another. When the ports are on different channels, this is really the cross talk between the channels.

In the recently posted article on the Test and Measurement web site, “Use S-parameters to describe crosstalk”, Alan Blankman and I review the properties of S-parameters which make them so suitable to cross talk and some of the features to look for in both the frequency domain and the time domain.

If you care about cross talk, you’ll want to check out this feature article.

“Most of the designs I get pulled into are really design rescues,” Jim Herrmann, Managing Partner & Principal Engineer at AppliedLogix, LLC, said at the 2012 IEEE EMC Global EMC and SI University.

From more than 25 years of hands on, practical design experience, Jim had an epiphany moment that the problems in all the designs he’s rescued have had four key root causes. He says, if you pay attention to these four key design concepts, you will avoid most of the signal integrity design problems in your next design.

Concept #1: Treat all interconnects as transmission lines and worry about their return paths as much as the signal paths. Always pay attention to the signal’s return path.

Concept #2: Try to engineer the transmission lines to look as close to a coax as possible, with the return path symmetrical around the signal path. Route in stripline, keep signals away form he edge of the board.

Concept #3: Forget the word “ground”. Board ground is just another piece of copper. Think “return path” and do everything possible to reduce the inductance of the return path.

Concept #4: Do everything possible to reduce the loop inductance of every element in the PDN. Drive out inductance in the PDN path.

Not a bad, concise list of important design guidelines to follow.

At the IEEE EMC Global EMC and SI University, Rick Hartley, a 47 year veteran of the circuit board design, SI and EMC industry, presented a short, personal account of a few of the more interesting problem boards he’s worked on over the years.

He offered a few gems of insight along the way.

“Its much easier to design a board that works the first time, and much harder to find a problem and fix it. Anything you do to fix a board after the fact is really just a band aid.”

“To control noise and EMI, we need to control containment of the electric and magnetic fields.”

He echoed the theme of the Global University: “Return paths are not just important, they are everything.”

When asked the difference between an SI problem and an EMC problem, he said, “An SI problem is when you step on your own toes. An EMC problem is when you step on someone else’s toes.”

Rick offered four examples of boards with problems, and the fixes which turned a crisis into a success.

Example #1: In a four layer board, low density board, the surface microstrip traces were referenced to a 5v plane, but no low impedance path was provided for the return current to get back to the 0v plane, connected to the driver.  He re-routed the adjacent plane to be the 0v plane, and EMI problem went away. Moral of the story: follow the return paths.

Example #2: In a high speed, multi layer board, the I/O section was carefully designed to minimize any common currents which could get out on the many 100 Mbps cables. As all the I/O were differential, the ground plane along the edge of the board was isolated from the board and only differential signals were allowed to cross the gap. But the board still radiated from the cables.

Then he noticed there were dozens of LED control lines that crossed the gap to light up the connectors. Even though they were “low speed”, they had just as fast an edge as the data. After adding low pass filters to the LED control lines, problem was eliminated. Moral of the story: “just because you think a line is low speed, doesn’t mean it is.

Example #3: “The best example of a the worst design.” The control board, with two processors and two memory banks was an 18 layer board. Many of the signal layers were filled with serpentines to keep the length skew between all the control to memory connections within 50 mils, even though the clock was 133 MHz.  To keep costs down, the 18 layer board had 4 signal layers between planes- difficult to control impedance and very high cross talk.

When he evaluated the timing, his team agreed that 300 psec was the timing skew they needed, which was a length skew of about +/- 1 inch. With this skew, the board routing could be reduced to only 10 layers, with two signals between planes, a more robust design. Moral of the story: overly tight constraints may increase the complexity of the board and introduce new problems.

Example #4: Taken from Lee Ritchey’s book, showed a 6 layer board, with large spacing between the power and ground planes, failing an EMC test. After copper fill was added to the signal layers, the board passed the radiated emissions test.

They say an expert is someone who has made all the mistakes possible. I always learn something listening to an expert. This is partly why this Global U is so valuable.

The second instructor at the IEEE Global EMC and SI University was Prof Tzong-Lin Wu, of the Dept. of EE, National Taiwan Univ. He flew in from Taiwan last night on a 22 hour flight to be here in Pittsburg, and showed no signs of jet lag.

While most of his presentation was setting the foundation of transmission line theory, he also spent time talking about return paths. This is the growing theme for this Global University. In particular, he offered a pop quiz to the 50 attendees.

He provided four different routing cases and asked our group, what would be the rating of each routed case, from best case to worst case?

Of course, the two extremes are obvious. Case 1 will be best and case 2 will be the worse.  After all, it’s important for the signal to never cross a split in the return path. But what about case 3 and 4? Which is worse, and by how much worse?

Our intuition may suggest that case 4 will be much worse than case 3. If the return path sees a continuous return, there should be little radiated emissions. So, shouldn’t case 3 be much better than case 4?

To show the impact of these four cases, Prof Wu shared simulations and measurements he has his students do at National Taiwan University.

Each of these four cases were built  in simple circuit boards and the radiated emissions measured by students. Their results are shown here.

Case 2, the signal crossing the gap, shows the most radiated emissions.

Case 4, with the signal hopping over small squares of holes in the return plane, creates the next most emissions. This was sort of expected. What is really interesting is that the case 1 and 3, with a continuous return plane, are identical. This says, even though there were gaps in the return path, but outside the width of the signal line, the gaps played no role in radiated emissions. It only takes a little web of continuous return path under the signal line to control the radiated emissions.

This was a great example of the dance between theory, measurement and simulation to illustrate the importance of return paths.

“Not all EMC rules are created equal,” Bruce Archambeault, a distinguished engineer at IBM and industry icon introduced as the theme of his tutorial at the Global University.

New to this year’s Global University is a focus on signal integrity in addition to the traditional EMC topics. About 60 engineers attended the 16 different tutorials from industry experts.

In the first session was on PCB Layout for EMC Compliance. The subtitle for Bruce’s session was really, “All about inductance and return paths.”

Bruce started out challenging us to question the relative importance of some of the many design rules we use in board design. “Should decoupling capacitors be close to the chip?” Yes, he says, but this is not the most important rule to pay attention to.

Instead, he says, paying attention to return paths of signals and the inductance of each path is probably the most important design rule to follow. The loop inductance of signal-return paths influence the switching noise in all high speed systems.  He went on to illustrate this principle by describing how geometry influences loop inductance and routing traces on aboard to control and minimize loop inductance.

Like a doctor who only sees patients with a medical problem and rarely talks to healthy people, I see hundreds of examples of S-parameter files either from measurements or simulations, all with some sort of problem.

I find one of the most common problems with these files is the port assignment. With four or more ports, there are multiple ways of labeling the ports. Two options are illustrated to the left.

While the quality of the information stored in the S-parameters is unaffected by the port labeling, how we interpret each S-parameter matrix element is strongly affected by the port labeling scheme.

For example, in one assignment, the insertion loss is the S21 matrix element, while in the other port assignment, the insertion loss is S31.

If you generate your S-parameter file using one assignment, but it is interpreted by someone else with the other port assignment, the analysis will be incorrect. Unfortunately, because so few users of S-parameters know what to look for in the S-parameters or are so afraid of looking at the actual data stored in the touchstone file, rarely is this root cause ever identified until too much time has been wasted.

Instead, I get a frantic call that the measurement and simulation is off, or that the eye predictions for a channel are completely collapsed, or that the model from their connector or package vendor shows that the signal is too small getting through the channel and how should they re-design the channel.

Following a few simple guidelines, this simple and common problem can be identified before it becomes a real problem and completely eliminated.

For more information on quick fixes to this problem, please see the paper that Alan Blankman and I wrote for Test and Measurement World, or check out the SPSI class I teach, which goes through this analysis in much more detail.

This question comes up in almost every advanced class I teach: what are the limits to FR4?

Like almost every important question in signal integrity, the answer always stars with “…it depends.”

The next step is to “put in the numbers” using analysis tools, based on all the assumptions and conditions for the specifics that should be considered.

In a long differential channel, if we do everything right, like no stubs anywhere, no asymmetry anywhere, no cross talk and no impedance discontinuities anywhere, the limitation for the highest data rate a channel can support is set by the signal to noise ratio (SNR) at the receiver.

While there are theoretical evaluations based on Shannon’s Information Theory about a channel’s information carrying capacity, its – 3dB bandwidth and the SNR at the receiver, there is an alternative analysis based on practical considerations.

If everything is done right in the channel, the fundamental limit to the data rate it will support will be set by the frequency dependent attenuation and how much signal is required for an acceptable eye . It’s not just the attenuation, it’s the frequency dependent attenuation. If we have roughly a linearly decreasing attenuation with frequency, much of this can be compensated using equalization techniques such as CTLE (continuous time linear equalization), FFE (feed forward equalization) or DFE (decision feedback equalization).

Typical high performance specs offer a limit of about –25 dB attenuation at the Nyquist frequency as the practical limit to what can be recovered in a usable eye. However, my buddies who work with optimized TRX equalization techniques tell me that if all the more than 10,000 coefficients available for the three equalization techniques are optimized perfectly, it may be possible to recover a usable eye with –40 dB attenuation at the Nyquist frequency.

Now we can ask, how far and at what frequency can you go in an FR4 interconnect and still have less than –40 dB attenuation? This is a simple analysis, which we go through in our S-parameters for SI (SPSI) class and Advanced Gigabit-differential Channel Design (AGCD) class. The result is a simple relationship between the length of the interconnect, in inches and the highest data rate, in Gbps, below which the attenuation will be less than –40 dB and an acceptable eye can be recovered. This relationship is:

This assumes the attenuation is limited to just dielectric loss and no conductor loss, which is the ultimate best that can be done. There is a distance-bandwidth trade off. This is fundamental and is the driver for transitioning to fiber optic connections at either high data rates or long distances. The boundary of when photons are more cost effective than electrons is set by this relationship.

Generally, the closer you get to this fundamental limits, the more expensive it becomes to implement a solution in copper and the more cost effective the solution may be in optical interconnect.

For example, in a 40 inch backplane, the ultimate limit to copper is about 20 Gbps. It is probably not practical to achieve 28 Gbps in a 40 inch backplane using a pulse amplitude modulation of two levels (PAM2), with an FR4 type material even with wide copper traces. Data rates above 20 Gbps using copper interconnects will require a lower loss laminate.

This estimate is not so far off from what is actually measured. Here are examples of the measured insertion loss for different length transmission lines in FR4 interconnects using wide conductors.

For the 40 inch interconnect, the frequency at which the insertion loss is larger than – 40 dB is about 10 GHz. This suggests the possibility of sending data at about 20 Gbps through this interconnect, close to what we estimated.

What’s the limit to copper interconnects in backplane applications? It depends. As a rough starting place, doing everything right, FR4 interconnects will limit out at about 20 Gbps in 40 inch backplanes. For higher data rates, and to have better margins, lower loss laminates will be in your future. It may be a possible to implement 40 Gbps backplanes in copper using suitable low loss materials.

There will be a limit to copper where it becomes more cost effective to switch to optical interconnects. I remember the days when folks suggested this limit was 2.5 Gbps. Then practical solutions in copper were developed. Then the limit was touted as 5 Gbps. But this was overcome. Then I heard the limit was 10 Gbps, but cost effective solutions were found.

As the cost of higher data rate copper channels goes up and the cost of optical channels comes down, they will cross and optical interconnects for 40 inches will be cost effective. I think this day is still in the future. To paraphrase Mark Twain, “the reports of copper’s death are exaggerated.”

Standing room only crowd at Eric Bogatin’s Speed Training Session, photo courtesy of Jeremy Graef.

DesignCon 2012 has come and gone, leaving in its wake a core dump of new and useful information that can be immediately applied to help solve signal integrity problems at the “bleeding edge” of bandwidth and data rate. Over the next few weeks, I will post a series of summary and review columns about what I learned at this DesignCon.

Let me start this series with one of my session, the Speed Training Event, How Return Loss Gets its Ripples. If you want a copy of the slides, you can download them here. If you missed the event, I covered this topic in a recent webinar on Reading S-parameters like a book. You can view the recorded webinar here. 

As an experiment, the speed training event was held on the show floor at the Chip Head Theater. Seating was limited to the first seventy folks, and the crowd spilled over into the aisles.

The theme of this presentation was to illuminate the basic, fundamental mechanism that leads to the ripples in all measured or simulated return loss plots. What is it about the interconnect structures under consideration that cause this distinctive feature, and why do ripples appear sometimes in insertion loss, but not other times?

The punch line is that it is all about the interference between the reflected waves from the ends of the interconnect- wherever there  is an impedance mismatch. In a uniform transmission line, this is usually at the ends of the line, where it connects to the 50 Ohms of the ports.

When the waves reflecting from the front interface and the back interface combine at the receiver, they will either constructively or destructively add together, depending on the total path length.

When the interconnect length is an even multiple of a quarter of a wave, they subtract and there is a minimum of reflected signal. When they are an odd multiple of a quarter of a wave, the reflections from the front of the interconnect and the back of the interconnect add and the reflected signal, the return loss, is a maximum.

The strength of the min and max signals depends on how large the impedance mismatch is, at that frequency.

If return loss and insertion loss are important properties of interconnects for your applications, you might want to check out the S-parameters for SI class I am teaching, now scheduled for Longmont, CO and San Jose CA in the next few months.

Hope to see you there!