Some folks like to learn from a live lecture to feel the energy of the speaker, while others like the feel of a solid book in their hands which they can skim for the kernels of insight immediately of value and skip the rest.

If you are in the latter category and are looking for good reference books on signal integrity topics, Prentice Hall has compiled a great collection of SI books.

In full disclosure, Prentice Hall is the publisher of two of my books, Signal Integrity Simplified and the second edition, Signal and Power Integrity Simplified. Even if they weren’t, I would be highlighting this wonderful series they have put together.

The Prentice Hall Modern Semiconductor Design Series is a collection of more than 40 books covering ASIC design, SOC design and signal integrity. While all of them are available as solid hardback books, some are now offered as ebooks.

The sub-list of just signal integrity topics lists more than a dozen books, focusing on a wide range of SI topics such as test, communications protocols, signal integrity, power integrity, jitter, de-bugging and timing analysis

Each book has been written by an expert in the field and together, represent the collected wisdom of the industry. You will not find a denser collection of signal integrity reference books anywhere.

If signal integrity is your thing, you’ll absolutely find something of value in this collection.

And if you are an expert in an area not already covered in this list, I know Bernard Goodwin, the series publisher, would be interested in talking you into adding to his series.

enjoy.

If your last product passed FCC certification and shipped on time, pat yourself, your EMC engineer and your design team on the back. You accomplished something that is really hard and doesn’t usually happen by accident.

Of the various EMC certification tests, the FCC Part 15 Class B, which applies to consumer products, is one of the most stringent. In the roughly 100 MHz range, the maximum allowed radiated emissions from your fully functioning product, when measured 3 meters away, within a 120 kHz bandwidth, must be less than about 100 microVolts/m.

To put this in perspective, what do you think is the maximum power a radio station could transmit, into a 120 kHz bandwidth, and still pass this FCC test? Is it 1 watt? 1 mwatt? 1 microwatt?

The answer is shocking. A radio station would have to radiate less than 10 nanowatts of power into a 120 kHz bandwidth, in order to pass certification. This is hard.

The most common reason for products to fail this test is due to radiation from common currents on external cables. For a cable 1 meter long, it only takes a common current of 3 microAmps to radiate enough to fail a certification test.

When you consider that a 1 volt signal, driving into a 50 Ohm line, is a signal current of 20 mA, you see that the common currents must be less than 0.01% of the signal currents. This is why passing EMC tests is hard.

I have yet to encounter a single large system company that does not have a horror story to tell of a product that worked great, passed all the functional tests, but either was never able to pass FCC certification or took so long to fix an EMI problem that its release was late and it missed the market window.

You don’t pass an FCC test by accident. It is by designing radiated emissions out of the product right from the beginning, and where you can’t design them out, you add filters and shielding to minimize their impact on the certification test.

Don’t expect to learn how to design a product to pass an EMC certification test by following a list of ten habits. But, if you want a list of topics to use as a guide to begin the discussions in your design team, here are my recommendations for the Top 10 Habits to follow to increase the probability of passing an EMC certification test:

1. Ground bounce drives common currents on external cables. Minimize ground bounce in all the components of your system
2. Use shielded cables. The shield of the cable should be an extension of the enclosure, not connected to the ground planes of circuit boards. Cable connectors should make a 360 connection between the shield and the enclosure.
3. All control wires and cables that leave the board, even if they are just routed inside the enclosure, should be routed with an adjacent return conductor. Use as long a rise time as you can afford for all signals that leave the board. Increase rise times with filters.
4. Use ferrites around the outside of external cables to suppress common currents.
5. Minimize mode conversion in all differential channels that leave the enclosure.
6. Add common signal chokes to all differential signals that leave the enclosure.
7. The largest source of noise, above 50 MHz, that gets into the power and ground network is from signals passing through the power and ground cavity. Manage this noise with return vias, differential signaling and decoupling capacitors adjacent to signal vias. Smart stack design up can enable the use of return vias.
8. Design the stack up so you can have power and ground planes on adjacent layers, with as thin a dielectric as possible, and preferably close to the board surfaces.
9. Plan on using a spread spectrum clock generator to smear the first harmonic of all signals into a wider bandwidth. The FCC receiver has a 120 kHz bandwidth. If you can spread the spectrum of each harmonic over 1.2 MHz, you reduce the average power detected in the FCC test by 10 dB.
10. Enclosure design is not about designing enclosures, it is about designing apertures and seams.

Bring these topics up in your next design review. Have your SI engineers and EMC engineers explain what they mean. If you are still not clear on the concepts, or how to implement them, read a book, find an expert or take a class.

If you weren’t aware of these guidelines when you designed and built your last product, you may have been lucky and dodged a bullet. Don’t rely on luck for your next design.

Inductance is probably the most confusing topic in signal integrity and one of the most important. It plays a significant role in reflection noise, ground bounce, PDN noise and EMI.

Since this topic is not taught in school in a way that is at all useful to help solve signal integrity problems, practicing engineers are force to learn about this critical topic from professional development courses, books or articles.

Two inductance books are now available which should be on every engineer’s bookshelf.

The original definitive book on inductance, Inductance Calculations, by Fredrick Grover, first published in 1946, is now available as a reprint. The newest book, Inductance: Loop and Partial, by Clayton Paul, was just released in 2010. These two books cover calculating partial and loop inductance of conductors in a wide variety of geometries. The approximations offered are both immediately applicable to calculating inductance values for cable, connector, packages and circuit board interconnect structures.

Inductance Calculations was published in 1946 by D Van Nostrand CO. It was then reprinted by Dover in 1948 and was out of print by the mid 1980s. It was just re-printed this year and is now available from Amazon in paperback for a very low price.

Motors, generators and rf components experienced a period of high growth in the 1940s. At their core were inductors and being able to calculate their self and mutual inductance using pencil and paper was critical (before the use of electronic calculators). While many coil geometries had empirical formulas specific to their special conditions, Grover took on the task of developing a framework of calculation that could be applied to all general shapes and sizes of coils.

While he did not explicitly use the term, what he calculates in his book are really partial inductances, rather than loop inductances. There is a raging debate in the industry today about the value of this concept.

Proponents say it dramatically simplifies solving real world problems and is perfectly valid as a mathematical construct. You just have to be careful in translating partial inductances into loop inductances when applying the concept to calculate induced voltages.

Opponents say there is no such thing as partial inductance, it’s all about loop inductance and if you can’t measure it, you should not use the concept. There is too much danger of misapplying the term.

Inductance: Loop and Partial, goes the next step in putting partial and loop inductance in perspective. Both terms are clearly articulated and defined. Many of the formulas Grover introduced are presented in Paul’s book, with the added benefit of the details of the derivations shown. In particular, the methods of combining partial inductances in parallel and series is introduced to show the connection between loop and partial inductances.

As Clayton Paul points out, there are many cases where partial inductance is an easier approach to solving inductance problems. In a pin field connector, for example, the return path may not be defined until after the pins are connected up in the circuit. Using the partial inductance matrix values makes this an easy circuit to simulate, while using loop inductance matrix values is a more complicated solution.

I personally am a big fan of partial inductance, and use it extensively in my book, Signal and Power Integrity- Simplified. It makes understanding the concepts of inductance easier, and highlights the three physical design terms that reduce the loop inductance of a signal-return path: wider conductors, shorter conductors, and bringing the signal and return conductors closer together. Most importantly, partial inductance is a powerful concept to aid in calculating inductance for arbitrary shaped conductors.

Inductance is fundamentally the number of rings of magnetic field lines around a conductor, per amp of current through it. In this respect, it is a measure of the efficiency for which a conductor will generate rings of magnetic field lines. To calculate the inductance of a conductor, it is a matter of counting the number of rings of field lines and dividing this by the current through the conductor. Counting all the rings surrounding a conductor is really performing an integral of the magnetic field density on one side of the conductor.

Literally everything about the electrical effects of interconnects stems from Maxwell’s equations. Paul and Grover start from the basic Biot-Savart Law, which itself comes from Ampere’s Law and Gauss’s Law, each, one of Maxwell’s equations, and derives all the approximations for various geometries. The Biot-Savart Law describes the magnetic field at a point in space from a tiny current element.

Using this approach, the authors are able to calculate the magnetic field distribution around a wide variety of conductor geometries and integrate the field (count the field lines) to get the total number of rings per amp of current. Using clever techniques of calculus, they are able to derive analytical approximations for many of these geometries.

The advantage of Pauls’ book is that the hidden steps in many of the derivations are outlined. Luckily, we don’t have to do the derivations ourselves, but can rely on the work of experts and we are then in a position to use the results.

A commonly used approximation is for the partial self inductance of a long straight, rectangular conductor, such as a lead frame in a QFN package or a connector pin. It is calculated as:

nH

Where
L = the partial self inductance in nH
B, C are the thickness and width of the conductor cross section in inches
Len = the length of the conductor in inches.

For example, for a 1 inch long lead, 3 mils thick and 10 mils wide, the partial self inductance is 23 nH. This is roughly 25 nH per inch, or 1 nH/mm, which is a common rule of thumb for the partial self inductance of a wire.

If you deal with connectors, packages, vias, board discontinuities or odd shaped transmission lines, and need to estimate the loop inductances of non uniform sections, these two books will be essential resources. You will have a great collection of inductance approximations at your fingertips.

Today, signal integrity has become the limiting factor in all products operating at 200 MHz and above. This includes all communications products, servers, personal computer and even cell phones. Not paying attention to signal integrity in the beginning of a design means the product may not work at bring-up.

While the highest end applications- telecommunications, test and measurement, super computers, mainframes and servers have been in this regime for more than thirty years, mainstream consumer products have been sensitive to signal integrity effects for only about ten years.

At the dawn of the “mainstream signal integrity” era, before “social networking” was even imagined, there was the SI-List. Almost all signal integrity engineers, at one time in their career, have participated on this email distribution list, either posting questions, answering questions, participating in the debates or listening to the chatter.

Sixteen years ago, on May 16, 1994, the SI-List was born with 30 members on the charter email list.

Ray Anderson, then a recent convert to signal integrity from years as a microwave engineer, came up with the idea of an email discussion group to continue the question and answer period from the last day of a four day short course he had taken on signal integrity.

He had recently joined Sun Microsystems as a signal integrity engineer. His jump start into this new field was “Electrical Modeling, Simulation and Design of Electronic Packages”, taught by Raj Mittra, Paul Franzon and Jose Schutt-Aine in San Jose, CA on May 9-12, 1994.

“On the last day of class I said it would be really neat if we put together a mail list to pose questions and answers to continue the discussions. I went back to my office on Monday and hacked together an email list on the SPARC2 worskstation sitting in my office at Sun Microsystems with the thirty names from the class.”

Figure 1. Ray Anderson in his package characterization lab at Xilinx, where he is currently a senior engineer.

Sixteen years later, there are 4,000 members on the SI-list spread over more than 34 countries. The range of participants starts with novices and students in college and extends to world renown experts such as Scott McMorrow, Steve Weir, Istvan Novak and Todd Hubbing.

“The typical questions posed to the list today, are not that different from the early days,” Ray says. “Over the 18 years I’ve been in signal integrity, the technology has changed, but the physics hasn’t.”

The questions posed on the SI-list are an indication of the most confusing or controversial topics in signal integrity. Power distribution design (PDN) has always been a hot topic. How many and what value decoupling capacitors do I need on my board and where should they be placed are the most common questions asked, followed by what is the inductance of a via?

Questions range from general, open ended topics, such as which is better a VNA or TDR? to specific design questions about the timing delay between data and clock in the DDR3 JEDEC timing spec.

The hot topic these days include the frequency dependence of the dielectric properties of laminates and the use of S-parameters to describe interconnect performance including causality and passivity.

“When I started the list and saw it grow so fast, I had visions of herding cats. But, it has turned out to be remarkably well self managed. Peer pressure usually establishes the norms for behavior,” Ray says.

In addition to questions and technical discussion, it is also a bulletin board for announcements about upcoming webinar, seminars, short courses or job announcements. List etiquette discourages recruiters from posting job openings in the SI field, except by the hiring manager directly.

There are always those who abuse the list. However, over the 16 years of its existence, there have only been 12 individuals banned from the list. One of the biggest frustrations with long time participants of the list is with the same, fundamental questions being asked by “newbies.”

“If you are going to ask a question,” Ray advises, “do your homework first. Make an attempt to solve the problem yourself. Read some books, search the web and the list archives, then pose the questions. Don’t just try to get someone to do your work for you.”

To subscribe to the SI-List, go to : http://www.freelists.org/webpage/si-list

To view the archives of postings, go to: http://www.freelists.org/archive/si-list/

Getting started with IBIS-AMI models? read on….

You cannot predict the performance of a high speed serial link without having an accurate model for the transmitters (TX), the channel, and the receivers (RX). These days, the channel model, ultimately represented by its S-parameters, is the easy part.

If you can describe a single differential channel in terms of the S-parameters from one end to the other, you can incorporate it into most simulators. This could be a touchstone file with an .s4p extension, for example, signifying a 4-port S-parameter data set.

Even better, if you can include the S-parameters for one or two adjacent channels, you can include the impact from uncorrelated channel to channel cross talk. This requires a .s8p or even a .s12p touchstone file.

But what about the TX and RX devices? IBIS models have been used to describe the TX and RX properties of devices which includes the switching rise time, output impedance, input gate capacitance, and even a simple RLC package model. However, in virtually all high speed link transceivers, equalization and clock recovery circuits are an integral part of the I/O circuitry. Up until now, there were no hooks in the IBIS model to include these features.

Extending IBIS models to include these “analog” features is the purpose of the IBIS-AMI(Algorithmic Modeling Interface) spec. The paper by Todd Westerhoff and his co-authors, presented at DesignCon 2010, “Predicting BER with IBIS-AMI: experiences correlating SerDes simulations and measurement,” provides a concise introduction to the features of IBIS-AMI models and some of the learning curve SiSoft and IBM went through to bring their simulation tools into excellent agreement.

This paper introduces the role of the AMI spec and alternatives to circuit simulation for link analysis. Under the IBIS-AMI umbrella, there are two parts to a link model: the passive channel, from the pads on the TX chip to pads on the RX chip and the serdes Tx/Rx analog characteristics. 

The impulse response of the channel, which can be obtained from the SDD21 response of the channel, can be used to predict the statistical properties of the eye directly, or with a convolution integral, calculate the transient waveforms at the receiver. No circuit simulation need be performed, just signal processing.

The second part of the AMI model is the algorithm to process the received signal. This can be how the impulse response is transformed by the equalizer into a new impulse response or how the transient waveform is processed by the equalizer. Even the behavior of how the clock recovery circuitry acts on the received transient waveform can be described in the algorithm.

The rest of this paper describes the correlation between IBIS-AMI models simulated in IBM’s internal simulation environment, which has been extensively verified with measurements, and the Quantum Channel Designer, the SiSoft link simulator environment. As seen in the figure above, at the end of their program, the agreement between the two simulation environments turned out to be very good.

If you would like a good introduction to IBIS-AMI models, this paper is a good starting place.

While it is possible to read a paper from the proceedings, there is much higher value in attending events where we can meet and greet. We often gain just as much when talking to another expert, as when discussing a design issue with a novice, or even a vendor.

DesignCon is the only conference specializing in SI. There are a few smaller events such as the EPEP conf, the Penn State SI Conference, and symposia such as the one I did with the IEEE EMC in Huntsville, Al. Some vendors put on their own one day events, such as CST, Agilent and Mentor.

There is now a new opportunity to add to our list. The IEEE MTT organization has been quietly building a presence in the SI world. Every year at the annual conference, the MTT usually has a one day workshop focusing on SI. These tend to focus on issues important at the very high frequency end- 5 GHz and above. I’ve had the privilege of presenting at many of the previous ones.

This year, Mike Resso and Brett Grossman have pulled together a sterling collection of presentations for the Signal Integrity Workshop, WSE, to be held on Sunday, May 23, 2010 at the Anaheim Convention Center.

The eight presentations planned are:

1. Paul Huray, University of South Carolina
“Bridging the Gap”

2. Michael Hill, Intel Corporation
“Microprocessor Power Integrity – Metrologies and Future Challenges”

3. Heidi Barnes, Verigy
“The Art of VNA Calibrations for Measuring Low Loss PCB Components”

4. Matthew Claudius, Intel Corporation
“End Use Model Correlation”

5. Bob Schaefer, Agilent Technologies
“Comparison of Fixture Removal Techniques for Connector and Cable Measurements”

6. Jim Rautio, Sonnet Software
“Measurement and Analysis of Substrate Dielectric Constant Anisotropy”

7. Evan Fledell, Intel Corporation
“Passive Interconnect Frequency Domain Characterization for Mixed-Medium and Vertical Interconnect Systems”

8. Leung Tsang, University of Washington
“Electromagnetic Modeling of High Speed Vertical Interconnect on Chip-Package-Board”

If you are involved in SI, I know you will find this program to be of great interest.

This was the title of a panel on which I was invited to participate at DesignCon 2010. Of all my DesignCon activities, preparing and presenting at this panel was the most fun I had.

Joining me on the panel were Gabe Moretti, owner of GabeOnEDA, Charles Pfeil, engineering director at Mentor, and the author of the wonderful book, BGA Breakouts and Routing, available for free download, and Gentry Lee.

Gentry has a long list of professional accomplishments. He is a chief engineer at the Planetary Flight Systems Directorate at the Jet Propulsion Lab, previously in charge of the Viking Mars Lander program and active on other planetary explorer missions like Galileo. He is also well known for his ten year collaboration with Carl Sagan on projects like the Cosmos series.

In addition, he has an equally rich background as a science fiction author, collaborating with Arthur C Clarke for ten years on the Rama series of science fiction books, authoring a total of eight science fiction books.

Gentry started the panel session with the perspective that “science fiction is about all things that are not impossible,” as contrasted with fantasy which is “that which cannot happen.”

He sees three important trends happening now which will have dramatic impact, one way or another, on our lives within the next fifty years.   

“We are in the biological revolution era,” he said, where we will design life as we want it to be. We do genetic engineering on food and animals right now to optimize them for our needs. He suggested that we are very close to enabling genetic engineering of our children.

He can imagine a time in the not too distance future where a couple goes into a doctor’s office, leafs through a catalog of features (online, of course) to select the qualities of their child. Maybe they would select a boy, red hair, blue eye, IQ of 132, interested in geology, with a gift for language and will play the piano. For a price, parents could customize the child they want and have their genes modified for the features.

Of course, we will be able to tailor medicines specific for our own personal biology and change any specific genetic defects we might have using a customized viral probe. Will this grant us effective immortality?

But, in this future, where complete biological engineering is possible, who will be able to afford it? Initially, for sure, it will be expensive, so will this future only be for the rich? Will that leave the rest of us at a greater and greater disadvantage? If access to this incredible enabling technology is only to the rich, will this cause even more polarization and friction in our society?

The second significant trend he sees is the decline and fall of the US as an economic power. More and more manufacturing sectors have left or are leaving the US. Design jobs in these areas will inevitably follow and right behind it, research and development. There go the skilled jobs. What will this leave as the economy base for America?

He suggests that companies looking to develop design tools in the electronics industry would do well to be working with the countries that will have the future designers, which probably will not be the US.

Finally, he notes the third important trend to be the growing influence of virtual reality for kids today. A number of studies have come out in the last two years indicating that more than 10% of kids between the ages of 13 and 23 spend more than 50% of their awake time living in a virtual world. This includes not just World of Warcraft like virtual games, but also interacting on the web, immersed in facebook and online communities.

The young of today choose to spend their time in a virtual world rather than the real world. Unfortunately, it seems that it is usually the brighter students who are the ones we are loosing to virtual alternatives. Some of them say the real world takes too long. Why spend weeks building relationships in the real world when you can go through the complete cycle of meeting, falling in love and falling out of love with someone in hours in a virtual world.

Will this be the end of civilization?

Charles presented a great perspective on virtual tele-presence, such as currently provided by Cisco. While the technology may be in place, will it really be a substitute for building a relationship? Will it ever be really possible to add the human element to a tele-presence meeting? After all, it’s the relationship that is the prime basis of all interactions.

I presented a brief perspective on where I see the future of man- machine interfaces heading. It may not be too far in the future when we have a functional wet-ware interface, a direct brain and electronics interface. When that happens, I might sign up for some extra ram and maybe even a co-processor. I recorded my talk and posted a copy of the slides, which are available for free viewing from my web site.

A good time was had by all!

Spring Institute of Signal Integrity Classes, April thru May 2010, San Jose, more info and online registration here.

One of my fun activities at DesignCon is getting to conduct 10-minute interviews with signal integrity stars. These are filmed by RealTime with DesignCon and posted on their website.

I did about 10 different interviews and other reporters with RealTime did another 20 or so interviews. If you missed DesignCon, or just want to see some of the new products, materials, tools and design solutions you might have missed, you’ll want to check out the posted interviews.

In particular, here are some of my favorites you’ll want to be sure to view:
Colin Warwick, Agilent, talking about their new 3D display. In addition to looking like a couple of really cool SI Dudes, we were able to see the results from a full wave EM field solver of current flow in a via field. With the LCD shutter glasses, and interleaved left-right screen being displayed on the monitor, it really did look like the vias were standing out in front of the screen. This 3D capability is embedded in Momentum and EMPro., able to show currents, fields and voltages.

 Joel Peiffer, 3M, talking about C-ply. 3M can provide thinner than 25 micron thick C-Ply laminates, sandwiched between copper planes. The dielectric is ground up Barium Titanate filled epoxy offering a Dk of 16-20. This is great for power and ground planes. The breakdown strength of the I mil core is more than 100 v. While Joel said these materials are in production and he has customers shipping their product with C-Ply, I could not get him to reveal any customer names. He just hinted that the early adopters are cell phone manufactures, and 10-15% of all cell phones are shipped with C-Ply.

Don DeGroot, CCN-I, talking about pcb materials measurements in his company. Don came from NIST, where he worked for 12 years as a researcher in the rf test group. He’s spun his experience in precision measurements into a company that performs contract materials measurements. He talked about the transitioning of NIST engineering techniques into a commercial business and how he does practical materials characterization.

Todd Westerhoff, SiSoft, talking about what’s new from SiSoft. At DesignCon 2010, SiSoft engineers gave 3 papers. One was on “When Shorter isn’t Better.” Todd described some problems where reflections in short tracks can cause problems, especially with resonances at specific lengths. If the traces are long enough some of these resonances may damp out and not be a problem. The danger, he says, in applying design rules is you may miss these length specific problems. This is why he advocates doing a post layout analysis.

To catch all of the RealTime interviews, check out their web site.

Spring Institute of Signal Integrity Classes, April thru May 2010, San Jose, more info and online registration here.

I presented a paper at this year’s DesignCon on the topic of causal models for materials. Whenever you go from a frequency domain description of a function into the time domain, you have to worry about causality.

Causality means a response can’t happen before the stimulus. This is the essence of cause and effect. The problem is that sine waves, and arbitrary combinations of sine waves in the time domain, are not usually causal. They extend back to minus infinity in time.

To make combinations of sine waves appear causal and be useful to describe time domain responses of real systems, we need to conspire the real and imaginary parts of the frequency domain response so all the waves at t < 0 cancel out leaving just stuff that happens after t = 0.

Any dielectric properties, described by the real part of the dielectric constant, Dk, and the ratio of the imaginary to the real, Df, must be causal, and so must have this relationship between their real and imaginary parts. This is described by the Kramers-Kronig relationship.

This means that “to know the real part of the dielectric constant is to know the imaginary part.” If we make the assumption that the real part decreases with the log of the frequency, then we can build a simple analytical expression for the dissipation factor Df.

We find that if the Dk drops with the log of the frequency, the Df will be roughly proportional to the slope of Dk and log F. This means the higher the dissipation factor the more dispersion.

It’s the dispersion that causes increased rise time degradation, above and beyond what we expect from just the losses. If your simulator does not include this frequency dependent dielectric constant, you will under estimate the rise time and actual performance may be worse than you predict.

If you care about high speed serial links and use FR4 like materials, you should care about frequency dependent material properties. In which case, here are three places for more information:

The webinar I am doing on Feb 25, 2010, will review this topic in great detail, and in a way that anyone can understand.

You can download a copy of the paper I wrote with my partners which was presented at DesignCon.

You can download a copy of the slides from this DesignCon presentation.

I am turning the DesignCon presentation into a video lecture. This will be posted on the web site in the next few weeks. Stay tuned!

Visit beTheSignal.com at booth #319. You’ll want to pick up a mug, an Appendix A -pocket guide to signal integrity design guidelines and, of course, some chocolate! Stop by and meet Susan and Laura. And I may have copies of my science fiction book, Shadow Engineer, on sale.

Monday, Feb 1, in the Theatre, I will present a 3 hour education forum, “Practical Magic: Signal Integrity Problems Disappear with the Right Tools“. My Agilent buddies and I will be showing about a dozen demos of some really cool hardware and software tools that I think should be in every signal integrity engineer’s tool box. check out my youtube video!

Tues, 8:30 am, I will present a paper “Frequency Dependent Material Properties: So What?”, with Don DeGroot, Sanjeev Gupta and Colin Warwick. If you are wondering about all the hype associated with “causal material properties” and want to know how does this apply to me, you’ll want to check out this talk.

Tues, 9:20, my colleague, Paul Huray, will present, “Impact of Copper Surface Texture on Loss, a Model that Works.” There’s a lot of buzz these days about rms roughness of copper. Come hear Prof Huray explain it’s really the surface texture of the copper, not just the rms roughness, that affects the extra losses from rough copper. You may find, as I discovered, that “everything you know about current and signal propagation is wrong.” Come hear the right way of thinking about how signals really propagate on interconnects.

Tues, 3:45 pm, I will participate on a panel discussion, “Science Fiction…is it really fiction?” This has got to be one of the more fun events at DesignCon, at least for me. I get to share the panelist table with Gentry Lee, famed co-author with Aurthur C. Clark of the Rama series, among other books, and noted scientist at JPL. We will talk a little about our visions of the future and open up the floor to discussion. Rumor has it, some of us might have books available for a book signing!

Wed 8:30 am. If you missed my education forum on Monday afternoon, you can catch it again on Wed morning.

I’m exhausted already, just writing about the exciting happenings at DesignCon 2010. See you there!