Dave, the Director of Signal Integrity Engineering at Molex, outline the process Molex uses in designing connectors for ultra high speed, where simultaneous mechanical and electrical requirements push the envelop of what is practical.

He outlined a five step process and walked through a few examples.

The first step is establish a few simple figures of merit or rules of thumb. For example, usually the design goal is at the Nyquist frequency of the application data rate. The specs for return loss are typically less than –12 dB and for near end cross talk, less than –40 dB.

The second step is generating concept mechanical and electrical models. These are the basis for stress-strain curves and initial electrical performance.

The third step is feedback from all the team- mold engineering, stamping, assembly tooling, plating and marketing. This cycle of concept design- multi-disciplinary review feedback and re-design, continues a few cycles until a near final design converges.

In the fourth step, the final design is released. This is the best approximation to what will deliver the performance, reliability and manufacturability requirements. When it costs more than $100k for a mold to test out a design, simulation analysis tools are leveraged to explore virtual prototypes, rather than using the build it and test it approach.

This means it’s important to have confidence in the analysis tools that they will accurately predict the measured performance of a part once built. A design of experiments (DOE) study of the virtual prototype is a key element. This identifies the most important design variables and where attention needs to be focused for robust manufacturing.

The fifth and final step is verifying the design and creating the deliverables. For many customers, the board design is just as important in determining the connector performance as the connector itself. Dave’s team provides engineering support to help customer optimize the board design based on the specific details of the connectors.

If you would like to hear the details of how Dave implements this process for the highest performing connectors in the Molex portfolio, you can watch the complete recording and download a copy of his slides on the www.beTheSignal.com web site.

While  you are there, you can also watch the recording of Jeff Loyer’s presentation from March 7, 2013.

If you are in Longmont, join us for the live Front Range Signal Integrity Seminar Series. All these events are always free. I hope to see you there!

The very first Front Range Signal Integrity Seminar was presented on March 7 by Jeff Loyer from Intel. He spoke on “State of the Art PCB Loss Control: What every user and fabricator needs to know”. If you missed this presentation, it was recorded and available for streaming on www.beTheSignal.com.

Jeff is an evangelist for the importance of loss control in circuit boards. His presentation at the Front Range Seminar recapped two of his recent DesignCon papers.

A few years ago, he introduced the SET2DIL technique to use a 2-port TDR to routinely measure the differential insertion loss of transmission lines, a technique suitable for a high volume manufacturing environment. Using this measurement and his modeling technique, he is routinely able to get good correlation, but had to watch out for two important traps: copper roughness and the DC resistivity of the copper.

Surprisingly, he found the DC resistivity of copper was not the typical 1.7 uOhm-cm value of pure copper that most fab vendors will tell you. It’s actually closer to 2.1 uOhm-cm. Using the wrong value of the bulk resistivity is going to start you more than 20% off in the modeled insertion loss for the conductor loss.

“If you want to get good correlation,” Jeff says, “you have to get the actual DC resistivity of the copper. This is not rocket science.”

The copper roughness is another term influencing the losses. For relatively smooth copper the Hammerstad approximation, integrated into many tools such as the Polar Instruments 2D field solver,  seems to work reasonably well. But for very rough, highly elongated copper (HLC), the impact of the roughness on loss exceeds the factor of 2 limit of the Hammerstad model.

In addition to what is important to worry about, he said, it’s important to also be aware of what is not important and does not influence insertion loss. Surprisingly, he found the vendor supplied data sheets for dissipation factor were usually adequate to predict the losses he measured.

If you care about insertion loss and the environmental influence on losses in low loss and high loss laminates, you’ll want to catch the rest of Jeff’s presentation, available here.

If you are in the Longmont, Co area, be sure to join us for the next Front Range Signal Integrity Seminar, scheduled for May 9, with Dave Dunham of Molex speaking about Designing High Speed Interconnects for 25Gb/s and beyond.

The topics will focus on connecting important problems with currently available solutions based on new designs, technologies, materials, services or products, presented by industry experts from around the world.

At each event the social hour, with appetizers and refreshments, starts at 5:30 pm and the presentation starts at 6:30 pm. There is no charge for any guest, but we do ask that those interested in attending sign up in advance so we can plan for adequate refreshments. Registration, directions and details for each presentation are available on www.beTheSignal.com.

In our on-line centric age of Twitter, Facebook, Linked-in, online universities, webinars and email, we think there is still a need for real-world, face-to-face, human-to-human encounters. After all, an essential ingredient to the success of any business is the personal relationships formed within a company, with customers and between peers in the industry.

While DesignCon and other professional conferences provide this important opportunity, not all engineers and business leaders can make it to these out-of-region events. The Front Range Signal Integrity Seminar Series offers a networking opportunity for professionals from local companies, businesses and universities.

We also recognize that not all engineers interested in attending an event will be able to make it, so each presentation will be recorded and later posted for free viewing on www.beTheSignal.com.

This series is fully funded by Bogatin Enterprises, a leader in Signal Integrity Training classes. A few tables are available for vendors to provide literature or product demos. Please contact Susan@beTheSignal.com to arrange for a table.

If you are interested in presenting at a Front Range Signal Integrity Seminar, drop a note to eric@beTheSignal.com.

Please help to spread the word about this lecture series to your colleagues and customers. We look forward to meeting you at a future presentation.

Reserve these dates for upcoming Front Range Signal Integrity Seminars:

March 7: Jeff Loyer, Intel

May 2: TBA

July 11; TBA

Oct 3: TBA

Dec 5: TBA (holiday party)

The experts who write many of these papers are still out there, but they are posting their white papers, application notes and presentations on their own web sites. I’ve started collecting links to these experts’ pages as a resource to identify top quality papers on signal integrity. You can find the list here.

This is a new landing page on my blog web site with a list of the experts, their web sites and some of the companies with a large selection of webinars and application notes available for viewing.

If you think I missed a good resource, please drop me a note offline and I will be happy to consider adding it to my list.

In this  project, I worked with Gordon Vinther at Ardent Concepts. They have a pretty cool interface, the Omniprobe-R, that enables contacting an array of micro coax cables to any footprint, like a BGA.

This can be used to either test an active BGA in a load board test application or when it is attached to a product board.

Their interposer technology can also interface between an array of coax cables and a high density array of pads on a circuit board. This sort of technology is essential when testing motherboards with high speed serial links.

In our paper, we looked at the high speed performance of two cable interfaces connected together with their compliant interposer. The 4-port measurements were done to 20 GHz using a Teledyne LeCroy SPARQ. We walk through these measurements and show how to interpret the results and display them in a way to get immediately useful information.

The punch line is that the Ardent interposer is pretty darn transparent. Check out the feature article for the details.

If you want to learn more about interpreting S-parameter measurements, you’ll want to check out the next S-Parameters for SI 2-day class we have coming up in late Feb 2013. Hope to see you there!

Tues: 1 pm in the ChipHead Theater on the show floor: A Potpourri of SI Puzzlers. Sometimes signal integrity effects are counter intuitive, confusing or even downright puzzling. In this 40 minute speed training event, we will take a look at 5 effects to puzzle over as a group. The effect or question will be presented, attendees will debate possibilities, and the right answer will be presented and reviewed. If you enjoy puzzles, want to be challenged or just want to enjoy the fun of solving important engineering challenges, come join us. For extra credit, bring your own puzzles to share.

Wed 9:20 am, in Ballroom F. Dramatic Noise Reduction Using Guard Traces with Optimized Shorting Vias with Bert Simonovich. Guard traces are sometimes used in high-speed digital and mixed-signal applications to reduce the noise coupled from an aggressor transmission line to a victim line. Sometimes guard traces are effective, and sometime they are not, depending on the topology and end connections to the guard trace. Optimized design guidelines for using guard traces in both microstrip and stripline transmission-line topologies are identified based on the mechanisms by which they reduce crosstalk. By correct management of the ends of the guard trace, a guard trace can reduce coupled noise on a victim line by more than 20x compared with the same design with no guard trace present. However, if the guard trace is not optimized, the crosstalk on the victim line can also be larger with the guard trace than without it.

Wed 11:05 am in Ballroom E, Which One Is Better? Comparing Options to Describe Frequency Dependent Losses, with Yuriy Shlepnev, Paul Huray and Don DeGroot. For any channel operating at 2 Gbps and above, conductor and dielectric losses can dominate channel performance. These effects must be included in any accurate system simulation. The problem isn’t that simulators don’t do this but that there are several choices in interconnect loss models, and it’s difficult to decide how to transform fab information into simulator input. There are different combinations of parameterized models for dielectric and conductor loss that are in popular use in the industry. Each model works to some extent. This session takes each model, explains its origin, compares its predicted insertion loss magnitude and phase with measured test traces, and then explores how the model scales in frequency and line width. This is useful when translating test coupon results into accurate simulation predictions.

Wed: 1 pm in the ChipHead Theater on the show floor: Ask the Experts…anything goes. Got Questions? Like, How many return vias should I use? Does it matter if the reference plane is 3.3v or Vss? Can I use a pigtail in my connector for USB 3.0? Why do we use 50 Ohms in our designs?   We’ve got answers. Rarely do you get a collection of industry experts together on the same side of the table, available to answer any SI or EMC question you may have. Join us for this unique panel discussion moderated by Eric Bogatin and bring your most pressing SI questions.

Our newest class, Hands on Workshop for S-Parameter Measurements (HOW-SPM), was created to teach these valuable measurement and analysis skills. We just finished our first class and it was a wonderful success.

This class was limited to only 12 students and filled up in the first 2 weeks after it was posted. Our next class on March 1, will also fill quickly.

Pairs of students shared a SPARQ, Signal Integrity Network Analyzer from Teledyne LeCroy, operating up to 40 GHz. All the principles and techniques we taught applied to ANY VNA. We limited attendance to 12 students total, so that everyone would get stick time and individual attention from our expert instructors. During the course of the day, everyone measured a variety of samples, each illustrating different measurement and analysis principles.

Resistors were used to illustrate how the measurement from a DMM at DC translated into the same resistance as obtained with a 40 GHz VNA- in the frequency and time domains.

A range of quality level 50-Ohm cables were measured to show the wide difference in bandwidth of good and bad cables, and the role of the connectors. We used port re-normalization to change the port impedances to view 75 Ohm cables and de-embedded the launches to show the impact at low frequency from the the port impedance, and the influence at high frequency from the connectors.

Don DeGroot of CNN Labs, designed and built a really cool test vehicle for the class. This board will be available for sale by CCN Labs in early 2013.

We looked at non-uniform and uniform lines with good and bad launches, in microstrip and stripline, as single ended and as differential. It was obvious looking at the first few measurements how strong a role the launches played above about 2 GHz. By de-embedding them low return loss measurements could be obtained up to 15 GHz, the limit to the $4 SMAs we used on the board.

One of the special exercises we did was to export the measurements from the test board as touchstone files and bring them into an analysis tool to extract the Dk and Df over frequency. All students saw that the Dk was strongly affected by the launches above about 2 GHz. This is one example where de-embedding is so important and why we focused an entire module just on how to perform fast and accurate de-embedding, and equally important, how to verify the quality of the de-embed file.

If you want to improve your VNA measurements, you really need to check out this class. Our next one is on March 1, in Longmont, CO. It will fill quickly so you’ll want to sign up early. Hope to see you there!

I read so many on-line forums where engineers- both novices and very experienced, ask some very important fundamental questions, and the responders struggle or muddle through the answers.

I tried to include the answers to many of these questions in my book. Here is a short list of 20 questions which are answered in detail in my text book. If you puzzle over some of these signal integrity questions, you might find it instructive to browse through my text book.

1. Why are signal integrity problems only going to get worse as we progress on Moore’s Law? (section 1.7)
2. Why is the bandwidth of a signal related to 0.35/RT? (section 2.10)
3. What is the origin of the rule of thumb that the bandwidth of a clock signal is roughly the 5th harmonic of the clock frequency? What are the underlying assumptions? (section 2.13)
4. What is the difference between a “real” component and an “ideal” circuit element and why is this distinction important? (section 3.3)
5. What is sheet resistance and why is this an incredibly useful figure of merit? (section 4.5)
6. Why is the capacitance of a simple, short wire hanging in space about 2 pF? (section 5.2)
7. What really is inductance and how is it influenced by physical design? (section 6.3)
8. What is ground bounce and how can I reduce it? (section 6.7)
9. Why does current in a conductor re-distribute at high frequency? (section 6.16)
10. What does characteristic impedance really mean? (section 7.9)
11. How does return current really flow in a transmission line? (section 7.13)
12. How does return current flow from one plane to another when the signal transitions through a via? (section 7.14)
13. Why are there reflections? (section 8.2)
14. Do corners cause reflections and when should I care? (section 8.16)
15. Where does dissipation factor and dielectric loss come from? (section 9.6)
16. Why are the capacitance matrix elements sometimes negative? (section 10.6)
17. What is differential impedance and how is it different from odd mode impedance? (section 11.7)
18. Why is there no far end cross talk in stripline? (section 11.11)
19. Why are there always ripples in return loss and sometimes in insertion loss? (12.11)
20. What is spreading inductance and why is this important? (section 13.14)

The flip answer is that if there were no reflected signal created when the instantaneous impedance the signal encounters changes, the universe would blow up. The reflected signal is created to keep the universe in harmony.

To see the problem, look at the figure to the left. The instantaneous impedance defines the ratio of the propagating voltage to the current in each region. If the instantaneous impedance in the two regions is different, the ratio of the voltages to currents in the two regions must be different.

Think about the incident voltage that hits the interface and continues to the other side. If there were no reflections, and the incident and transmitted voltages were different, there would be an electric field between two points on either side of the interface. The closer these two points get, the larger the electric field.

If we bring the two points really, really close but still sitting in the different impedances, the field could become extremely large, and the universe could blow up.

So, maybe the voltages have to be the same. But, if the impedances are different, the ratios of the voltages to the currents in the two regions have to be different different. If the voltages are the same, the currents into the interface must be different. But, if there is more current going into the interface than transmitted out, charge will build up and if we wait long enough, the universe will explode at the interface.

These two conditions, of the voltages being continuous and the net current into the interface being 0, are called boundary conditions. They cannot both be met without a reflected signal being created. The details of how the reflected signal helps to keep the universe in harmony and the derivation of the reflection coefficient and transmission coefficient can be found in the brief article I wrote for PCD&F magazine.

So we see that the most common signal integrity problem, the creation of reflections from impedance changes and the signal distortion that results from multiple reflections, is really a good thing. Without it, the universe would blow up.

To various extents, the coupling between aggressor and victim channels depends on the signal rise time, coupled lengths, interconnect density and line impedances. But not all system simulators take into account all the couplings which can cause problems. This is why it is sometimes important to measure the channel to channel cross talk.

S-parameters provide a natural way of characterizing cross talk between channels because each term in the S-parameter matrix really describes the coupling of one port into another. When the ports are on different channels, this is really the cross talk between the channels.

In the recently posted article on the Test and Measurement web site, “Use S-parameters to describe crosstalk”, Alan Blankman and I review the properties of S-parameters which make them so suitable to cross talk and some of the features to look for in both the frequency domain and the time domain.

If you care about cross talk, you’ll want to check out this feature article.