Eric Bogatin's Blog: What I Learned This Month

I always like to ask attendees to my EPSI class what is their favorite guideline for selecting decoupling capacitors for each power pin of a package.  I typically hear one of two answers. It’s always select three capacitors, but half the group says each one is the same 0.1 uF value, while the other half says make them 0.1 uF, 0.01 uF and 0.001 uF. Which is the better one?

The most common answer to all signal integrity questions is, “it depends”. In this case, it depends on the device being decoupled, the thickness of the power and ground plane cavity, the size of the board and what might be going on inside the package and on-chip. To arrive at a great answer, you need all this information and then need to simulate.

However, often times, “an OK answer NOW! is better than a great answer late.” If you have to choose, which approach is better?  At first glance, we might expect more capacitance is always going to be better, so picking all three capacitors to be the same value is the way to go. However, the goal in designing the power delivery network (PDN), is to keep the impedance below the target value across the bandwidth of the application. The interactions with the capacitors and planes will often create a second order problem which different capacitor values can solve.

A simple SPICE simulation answers this question for us. The adjacent plot shows the simulated impedance profile a single power pin would see looking into the planes with 3 different capacitors attached.  The blue trace is with all three capacitors having the same 0.1 uF value. The red trace shows the impedance profile with three different values, of 0.1 uF, 0.01 uF and 0.0027 uF.

Even though the three identical capacitors have a larger total capacitance, the parallel resonance they create with the plane capacitance, causes the large parallel resonant peak. Using three different value capacitors suppresses this peak and keeps the impedance below the target value, shown in the black line.

If you want to get a slightly better impedance profile, select the lowest value capacitor to have a self resonant frequency (SRF) the same as the parallel resonant frequency of the inductance of the three capacitors and the capacitance of the planes. This translates to  Clowest = A/(3 x h), with h the cavity thickness in mils, A, the area of the board planes in sq inches and Clowest in nF. For this example, A = 25 sq inches, h = 3 mils and Clowest = 2.7 nF.

Want to learn the details of optimizing the PDN? come to our EPSI or HSDP class, or check the web site, www.beTheSignal.com to view some of the online lectures on power integrity design.

I’m backlogged in my reading and just now finished the Dec 2007 issue of IEEE Trans on Components, Packaging and Manufacturing Technology, Part A: Packaging Technologies. There I came across another article by Len Schaper from Univ of Arkansas in Fayetteville.

Len introduced the idea of a stealth capacitor more than 10 years ago, as a very low inductance component for solving power integrity problems. As anyone who has taken my EPSI class knows, the three knobs to reduce the loop inductance of any element in the power delivery path is keep it short, use wide planes and with both planes close together as possible.

Len’s stealth capacitor leverages these three design features by using a very thin dielectric of Ta2O5 between conductor plates. This layer can be about 2,000 Angstrom’s thin, and with a Dk of about 23, it is capable of about 100 nF/sq cm. In his paper, he presents a process for making this multilayer, increasing the capacitance per unit area up to as high as 600 nF/sq cm.

Since the current flows in opposite directions in the two plates, the loop inductance can be kept extremely low. The example here, taken from his paper, shows an ESL on the order of 30 pH. I think this sort of thin film, embedded technology has a lot of potential where it can be integrated either directly on chip or in the package, leveraging its ultra low impedance at very high frequency.

Last week, I was in Montreal for the IPC Educational Course and Technical Conference and spoke with John Andresakis from Oak-Mitsui. He gave a talk on Copper Foils for High Frequency and Fine Pitch Applications. Though I was not able to attend his talk, I spoke with him after wards and learned about the incredible progress in producing smooth copper foils for low loss interconnects.

It’s easy to estimate the conductor losses in copper traces. It’s based on the line width, the skin depth and the frequency. This topic is covered in detail in our new course, High Speed Design Principles. When the surface roughness of the copper is larger than the skin depth, the series resistance from each surface can be increased by about a factor of 2. In stripline, this means surface roughness can increase series resistance by about 50% from the loss expected with ultra smooth copper traces.

With a typical RMS roughness of about 5 microns, the series resistance of each surface is doubled at frequencies above about 500 MHz. Surface roughness has the effect of increasing the losses of a 5 mil wide line to appear as lossy as a 3.5 mil wide line.

Enter a new generation of ultra smooth copper foil, DFF (dual flat foil). John said that the process Oak-Mitsui developed creates the smooth copper as it is being plated on the drum from the solution. The smoothness arises from careful control of grain size during the plating process. John said DFF copper foil can have a smoother surface on the solution side than on the polished drum side.

The smoother copper foil from Oak Mitsui can’t reduce the copper losses below the theoretical limit, but it can give back the 50% resistance increase lost through roughness. For high speed series links pushing the loss limits, or using low loss lamiantes such as RO4350, this ultra smooth copper has a lot of potential.

I wrote a column in 2001 on the first commercial use of high temperature superconductors (HTS) and have followed the technology since its creation in 1987. It was with great interest I read about a superconducting power transmission cable installed in Long Island, NY. This is a joint project between the Long Island Power Authority (LIPA) and the American Superconductor Corp (ASC). It was commissioned on April 22, 2008.

The cable is basically a pipe for liquid nitrogen with layers of high temperature superconductor (HTS) and insulation wrapped around the outside. As a power transmission system, the voltage rating is 138 kV, carrying 574 MegaWatts. This comes out to about 4kA. It’s only 2,000 feet long, but is a start.

While transmission losses from IR drop are typically 7-10% of the power transmitted, superconducting cables are lossless in principle. However, there is still the energy used in refrigerating the cable. There is a lot of room for improvement in insulation and heat pipe design, so in the long term, superconductor cabling for power transmission will be an important element to a large sacle, efficient power distribution network.

I visited Neoconix last month. They have a novel interposer technology which turns any PCB surface into a compliant, probing surface. On a separate sheet, an array of bent leads is manufactured. This sheet is laminate to the surface of a circuit board with landing pads to match the footprint of the beams.

The composite board is plated up so that the plating provides the electrical connection between the attached beam and the substrate. With this approach, the compliant beams can be placed on one or both sides of the board. The board can be a simple array of through hole vias connecting one side of the board to the other, or have functionality, like power and ground planes, decoupling capacitors, or a geometry transforming footprint.

For a while, I’ve been promoting the idea of integrating geometry transformers for test sockets to relieve the interconnect burden from load boards. In testing devices with pads or leads on 0.5 mm centers or finer, you pay a premium for the load board to get the fine pitch required by the socket. For 0.4 mm, the yield of the load board is so low, you have to build 3 or 4 boards to get one that is not shorted.

Why not have the fine pitch for the device on one side of a small interposer board and a coarse pitch for the board surface on the other side, with a multilayer circuit board providing the fan out? Even a 4 layer board could have controlled impedance fan out, with low impedance power and ground distribution. I think Neoconix technology is the perfect solution to implement this cost effective approach.