Published by Eric Bogatin on 28 Jul 2008
I always like to ask attendees to my EPSI class what is their favorite guideline for selecting decoupling capacitors for each power pin of a package. I typically hear one of two answers. It’s always select three capacitors, but half the group says each one is the same 0.1 uF value, while the other half says make them 0.1 uF, 0.01 uF and 0.001 uF. Which is the better one?
The most common answer to all signal integrity questions is, “it depends”. In this case, it depends on the device being decoupled, the thickness of the power and ground plane cavity, the size of the board and what might be going on inside the package and on-chip. To arrive at a great answer, you need all this information and then need to simulate.
However, often times, “an OK answer NOW! is better than a great answer late.” If you have to choose, which approach is better? At first glance, we might expect more capacitance is always going to be better, so picking all three capacitors to be the same value is the way to go. However, the goal in designing the power delivery network (PDN), is to keep the impedance below the target value across the bandwidth of the application. The interactions with the capacitors and planes will often create a second order problem which different capacitor values can solve.
A simple SPICE simulation answers this question for us. The adjacent plot shows the simulated impedance profile a single power pin would see looking into the planes with 3 different capacitors attached. The blue trace is with all three capacitors having the same 0.1 uF value. The red trace shows the impedance profile with three different values, of 0.1 uF, 0.01 uF and 0.0027 uF.
Even though the three identical capacitors have a larger total capacitance, the parallel resonance they create with the plane capacitance, causes the large parallel resonant peak. Using three different value capacitors suppresses this peak and keeps the impedance below the target value, shown in the black line.
If you want to get a slightly better impedance profile, select the lowest value capacitor to have a self resonant frequency (SRF) the same as the parallel resonant frequency of the inductance of the three capacitors and the capacitance of the planes. This translates to Clowest = A/(3 x h), with h the cavity thickness in mils, A, the area of the board planes in sq inches and Clowest in nF. For this example, A = 25 sq inches, h = 3 mils and Clowest = 2.7 nF.