What I Learned this Month

To paraphrase Heraclitius of Ephesus (535 BC – 475 BC), “The only constant is change.” This mantra has driven the electronics world since the inception of the tube in the early 1910’s. The latest advance in 3D chips may be a glimpse into the next wave for electronics.

We usually hear about the active part of the system as what drives the advance of electronics, but the interconnects have played just as vital a role in increasing functional density in the last nearly 100 years. It can be argued that the interconnects have even lead advances in the active components.

The vacuum tubes used discrete wiring. They evolved into the transistor. The printed circuit board was created to increase the functional density of discrete transistors. The integrated circuit miniaturized the circuit board interconnects and enabled orders of magnitude increases in functional density and launched the treadmill of Moore’s Law.

In this phase, we evolved an alphabet soup of individual package styles: DIP, PQFP, PGA, LGA, BGA, CSP. Circuit board technology evolved to micro vias and HDI to keep up with the interconnect density demands of the CSP introduced in the early 1990s. I’ve written three books and numerous articles on these technologies.

Packaging technology took the functional density lead with the introduction of the multi-chip package. One packaged component had the functional density of a chip two or three silicon-generations away. IC technology followed in packaging’s footsteps with the System on a Chip (SoC) and multi-core processors. And multi-chip modules changed its name to System in Package (SiP) to sound cooler.

However wonderful the advances of SoC and SiP are to advance functional density, they will always live in a planar world,  limited to one or at most, two surfaces. Packaging technology allowed close to 100% packaging efficiency, but it could never exceed what the silicon was capable.

Packaging technology took the lead in breaking the bounds of the 2D world, with stacked chips. Starting with flash and SRAMs for cell phones, there are no fundamental limits to stacked die modules. The packaging efficiency exceeds 400% in some applications.

While silicon technology has made small forays into the 3D world, with laminated silicon layers and  thru-silicon-vias, such as this IBM illustration shown to the left, none of them have shown legs…until this recent announcement of 3D integrated circuits.

The first 3D chip is running at 1.4 GHz at the University of Rochester. This is not a collection of stacked layers, it is an integrated design specifically optimized for 3D with all key processes functioning vertically through multiple layers of processors.

“I call it a cube now, because it’s not just a chip anymore,” says Eby Friedman, Distinguished Professor of Electrical and Computer Engineering at Rochester and co-creator of the processor. “This is the way computing is going to have to be done in the future. When the chips are flush against each other, they can do things you could never do with a regular 2D chip.”

Of course there are challenges ahead, but that’s exactly what was said at the beginning of the IC era. Functional density in 2D will always operate at the most cost effective point of the integration vs yield curve.  This defines the largest chip possible. Packaging technology will always give the silicon the next boost in functional density. But now, there is a glimpse of how silicon technology might be able to jump to the next level of functional density by growing in the third dimension.

“Are we going to hit a point where we can’t scale integrated circuits any smaller? Horizontally, yes,” says Friedman. “But we’re going to start scaling vertically, and that will never end. At least not in my lifetime. Talk to my grandchildren about that.”

Want to read more about the dance between packaging and silicon technology, check out the columns and feature articles on my web site, www.beTheSignal.com.

I noticed that Agilent is offering a slew of live signal integrity events in the next month.

From Sept 16 – Oct 17, there is the  “High-Speed Digital Seminar – Tackling High-Speed Serial Designs“. This is a series of presentations on SI issues, like DDR, PCIe, PLLs, Gbps FPGAs and VNA and TDR techniques. If you don’t know what the TLAs and FLAs*** are, this seminar is probably for you.  This is like a what’s what in SI today. Though it is moving around to six different locations, I am disappointed that I will not be around to catch any of them! I hope Agilent makes the talks available on a CD.

On Sept 22, there is a 1-day event, Interconnect Analysis and Modeling Workshop. This looks like it covers the use of TDR, VNA, PLTS and ADS for SI applications. Lots of instrument and simulation demos for sure.

On Oct 21-24 there is a 3-day hands on workshop, Designing for Signal Integrity with ADS. This is a soups to nuts class on getting started with ADS for SI applications. For those of you who have tried to get up to speed on ADS on your own, it is a little confusing. All you need is about 30 minutes with someone showing you the style of ADS simulations and you will see it is simple and straight forward.  This class can give you a jump start to accelerate you up the learning curve of being productive with ADS.

***ok, TLA is Three Letter Acronym and FLA is Four Letter Acronym

Pencils down! The results of the latest pop quiz are in. The question posted on www.beTheSignal.com a few weeks ago was “A data stream has a 10-90 rise time of about 300 psec. What is the approximate bandwidth of the signal?”

There were 303 answers submitted. Our web site assures that a person can submit only 1 answer.  70% of you got it correct.

The bandwidth of a signal is the highest sine wave frequency component in eh signal. As a pretty good approximation, the bandwidth of a signal is about 0.35/RT, where RT is the 10-90 rise time.

In this example, the rise time is 0.3 nsec, so the bandwidth is about 0.35/0.3 = 1 GHz. Of course, this assumes a linear or gaussian edge shape. If it is grossly distorted, or has a long tail, such as with a lossy line, the 10-90 rise time can be long, and this approximation would be an under estimate.

The use of the term bandwidth is always only a rough approximation. If it is important whether the bandwidth is 1.1 GHz or 1.3 GHz, don’t use the bandwidth, use the entire spectrum. Want to know more about rise time and bandwidth, see chapter 2 in my book, or attend the EPSI class.

For you puzzle geeks, a new pop quiz has been posted! The answer will appear in this blog in a few weeks.

I was not able to attend the EMC 2008 Symposium in Detroit last month, but I did take a look at some of the papers.  One in particular caught my eye: “Signal Integrity Analysis of a 26 Layer Board with Emphasis on the Effect of Non-Functional Pads”, by Anthoni Ciccomaanccini Scogna, with CST.

Do vias look inductive or capacitive? What is the most common answer to all signal integrity questions? “It depends”. Anthoni does a nice job of showing that by adjusting the non-functional pads (NFPs) in vias with adjacent return vias, you can switch a long via from looking capacitive to looking inductive. There is a “Goldilocks” solution somehwere in between.

It is pretty well know that non-functional pads increase the capacitance of a via and especially for long vias, makes their impedance a little low. This degrades their bandwidth. Removing non-functional pads will usually bring the impedance up, closer to 100 ohms differential.

Anthoni use a 0.32 inch thick backplane as a test vehicle to explore this question of whether the NFPs should be removed or not. He took a cookie cutter section from the backplane board, containing  two pairs of differential vias with associated, adjacent return vias. The cross section is shown to the left, for just one of the differential pairs. The colors also show the current density for a common signal.

He brought the 3D physical model into CST, a 3D full wave solver. He then used his tool to calculate the differential return and insertion losses, in both the frequency domain and time domain, for a signal going from the top surface, through a very long via to a layer near the bottom of the board.

With a way of predicting performance, he was able to go into the design and remove all the non-functional pads.  The best comparison is in looking at the simulated TDR response through the differential pair, for the case with the NFPs and when they are removed.

He found that with the NFPs, the response looked very capacitive, while after the NFPs were removed, the via path looked a little inductive.  In the TDR plots to the left, the blue trace is with the NFPs, while the pink trace is with the NFPs removed.

The answer he gave to the question of whether to remove the NFPs was the most common answer to all SI questions: It depends.

In general, removing the NFPs makes the via inductive.  While it is closer to 100 ohms differential than with the NFPs, it has room for improvement. He concludes that if you really want to optimize your via design, you probably want to use a 3D field solver to find the right combination of clearance hole and NFP size to bring the via closer to 100 Ohms.

I would add that the residual stubs present in all vias tends to move the vias toward the capacitive side and even with all the  NFPs removed, most long vias will look capacitive. If you are not going to run your own 3D simulation, I think, as a good design guideline, remove your NFPs.

If you are interested in via design, this is one of the topics covered in our High Speed Design Principles Class (HSDP).  Check the web site for the scehdule.