Published by Eric Bogatin on 16 Sep 2008
To paraphrase Heraclitius of Ephesus (535 BC – 475 BC), “The only constant is change.” This mantra has driven the electronics world since the inception of the tube in the early 1910’s. The latest advance in 3D chips may be a glimpse into the next wave for electronics.
We usually hear about the active part of the system as what drives the advance of electronics, but the interconnects have played just as vital a role in increasing functional density in the last nearly 100 years. It can be argued that the interconnects have even lead advances in the active components.
The vacuum tubes used discrete wiring. They evolved into the transistor. The printed circuit board was created to increase the functional density of discrete transistors. The integrated circuit miniaturized the circuit board interconnects and enabled orders of magnitude increases in functional density and launched the treadmill of Moore’s Law.
In this phase, we evolved an alphabet soup of individual package styles: DIP, PQFP, PGA, LGA, BGA, CSP. Circuit board technology evolved to micro vias and HDI to keep up with the interconnect density demands of the CSP introduced in the early 1990s. I’ve written three books and numerous articles on these technologies.
Packaging technology took the functional density lead with the introduction of the multi-chip package. One packaged component had the functional density of a chip two or three silicon-generations away. IC technology followed in packaging’s footsteps with the System on a Chip (SoC) and multi-core processors. And multi-chip modules changed its name to System in Package (SiP) to sound cooler.
However wonderful the advances of SoC and SiP are to advance functional density, they will always live in a planar world, limited to one or at most, two surfaces. Packaging technology allowed close to 100% packaging efficiency, but it could never exceed what the silicon was capable.
Packaging technology took the lead in breaking the bounds of the 2D world, with stacked chips. Starting with flash and SRAMs for cell phones, there are no fundamental limits to stacked die modules. The packaging efficiency exceeds 400% in some applications.
While silicon technology has made small forays into the 3D world, with laminated silicon layers and thru-silicon-vias, such as this IBM illustration shown to the left, none of them have shown legs…until this recent announcement of 3D integrated circuits.
The first 3D chip is running at 1.4 GHz at the University of Rochester. This is not a collection of stacked layers, it is an integrated design specifically optimized for 3D with all key processes functioning vertically through multiple layers of processors.
“I call it a cube now, because it’s not just a chip anymore,” says Eby Friedman, Distinguished Professor of Electrical and Computer Engineering at Rochester and co-creator of the processor. “This is the way computing is going to have to be done in the future. When the chips are flush against each other, they can do things you could never do with a regular 2D chip.”
Of course there are challenges ahead, but that’s exactly what was said at the beginning of the IC era. Functional density in 2D will always operate at the most cost effective point of the integration vs yield curve. This defines the largest chip possible. Packaging technology will always give the silicon the next boost in functional density. But now, there is a glimpse of how silicon technology might be able to jump to the next level of functional density by growing in the third dimension.
“Are we going to hit a point where we can’t scale integrated circuits any smaller? Horizontally, yes,” says Friedman. “But we’re going to start scaling vertically, and that will never end. At least not in my lifetime. Talk to my grandchildren about that.”
Want to read more about the dance between packaging and silicon technology, check out the columns and feature articles on my web site, www.beTheSignal.com.