Published by Eric Bogatin on 30 Nov 2008
This pop quiz question on www.beTheSignal.com, was really about estimating the equivalent series inductance (ESL) of a decoupling capacitor and how low it can be engineered. Of course, the ESL is all about how the capacitor is integrated into the board and the stack up of the board.
As a rough approximation, the ESL of a capacitor is composed of three elements, the sheet inductance of the capacitor and surface traces, the via loop inductance to the top of the power and ground plane cavity and the spreading inductance in the power and ground plane cavity. Each of these can be estimated with simple approximations.
The sheet inductance of the surface traces and the capacitor body is 32 pH/mil x h1 x Len/width
h1 = distance from top surface to top of the power-gnd plane cavity, in mils
Len = the total length of surface traces and capacitor body, in mils
width = width of the surface traces, in mils
The ratio of Len/width is really the number of squares of surface trace, and 32 pH/mil x h1 is the sheet inductance per square between the board surface and the top of the power-gnd cavity. If h1 = 5 mils, the sheet inductance of the top layer is 160 pH/square. If there are 5 squares of surface traces, this is a total loop inductance from the surface traces of about 800 pH.
The loop inductance of the vias to the top cavity is about 15 pH/mil. For a total of 5 mils, this is about 75 pH.
Finally, the spreading inductance in the planes is about 20 pH/mil x h2 x ln(B/D), where
h2 = the distance between the power and ground planes, in mils
B = the distance between the capacitor and the BGA package pins, in mils
D = via diameter in mils.
If h2 = 3 mils, a common minimum thickness in all fab houses, and B = 500 mils and D = 13 mils, the spreading inductance is roughly 20 x 3 x 3.6 = 220 pH
Without doing anything special, the typical ESL of an 0603 multi layer ceramic capacitor (MLCC) might be on the order of 800 pH + 75 pH + 220 pH = 1.1 nH. The choices were 0.2 nH, 1.5 nH and 5 nH. the closest to our simple estimate is 1.5 nH.
Of course, if you do everything right, bring the power-gnd plane cavity close to the surface, use a minimum number of squares for surface traces, use a thinner power-gnd plane cavity, the ESL can be dropped even more. If you use interdigitated capacitors, like the X2Y, the parallel combination of capacitor elements can reduce the surface trace inductance and reduce the spreading inductance in the cavity to achieve an ESL on the order of 0.2 nH.