Published by Eric Bogatin on 30 Dec 2008
Colin Warwick invited me to write a post for his blog. I got so many comments about it, I decided to post it here as the end of year closer. Here it is:
We microwave minute rice to cook it faster. We get our news from the one liners of late night talk show comedians. In this perspective I give a talk, as a distinguished lecture for the IEEE EMC society, on “The 10 habits of highly successful board designers.” Everyone is welcome to download a copy of my presentation. I’ve since created a list of the top 10 design habits specifically for highs peed serial links. If you get your philosophy of life from bumper stickers, then you’ll want to design your boards based on these ten rules. Here they are for your entertainment (BR is the bit rate in Gbps):
1. use as low a differential impedance as you can get away with
2. keep the differential impedance of signal lines constant by adjusting line width when the coupling changes
3. use tightly coupled differential pairs when interconnect density is critical, use loosely coupled differential pairs when loss is over riding
4. keep the length skew between the lines in a pair less than 60 mils/BR
5. when possible, route the signal lines off axis from the glass weave
6. minimize the discontinuity of DC blocking capacitors by using the minimum size capacitor pads and use cut outs in the nearest ground plane when the pad width is larger than the surface trace width
7. keep the length of via stubs, in mils, as short as possible, and no longer than 300 mils/BR.
8. increase the impedance of vias by removing NFPs and use as wide a clearance hole as you can get away with
9. use a return via adjacent to all differential signal vias
10. use pre- or de- emphasis on TX and equalization on the RX
11. bonus pointer: ask your fab vendor for smoother copper
For more information about designing high speed serial links check out www.beTheSignal.com.