Eric Bogatin's Blog: What I Learned This Month

If you work with differential pairs, check out our first No Myths Allowed Webinar, Feb 25, Practical Differential Pair Design.

In preparing the content for our new course on Power Distribution Network Design (PDN), I’ve been reviewing many of the capacitor vendor web sites to see how they describe the electrical properties of their capacitors.

I have found in measuring many capacitors that an RLC model is a pretty good approximation to the actual, measured impedance of a capacitor, even into the GHz range. The C is based on the internal design of the capacitor, the number of plates, their spacing and the ceramic used. The value I measure usually does meet the specified value to within the typical 20% tolerance.

The R is also intrinsic to the capacitor inner design and depends on the series resistance of the metallization in the plates. The higher the C, the more plates in parallel and the lower the R. I typically measure the R to be within 30% of the specified value.

However, the most important quality of a capacitor for use in decoupling applications is its equivalent series inductance or ESL. The ESL is not intrinsic to the capacitor, but depends on how it is mounted to the circuit board.

Yet, every capacitor vendor site I visited lists a value for the ESL of their capacitors. AVX uses a value of 0.4 nH while Kemet uses a value of 0.7 nH. When pressed, they say this is the “intrinsic” ESL of their capacitors. This has as much meaning as the sound of one hand clapping, and for basically the same reason.

While it is perfectly correct to say the “partial self inductance” of a capacitor is 0.4 nH, unless you also know the partial self and mutual inductances of the rest of the elements that make up the loop the capacitor is part of, you can’t do anything with this term, and I doubt that AVX or Kemet mean to present their inductance as a partial self inductance.

From a user’s perspective, what is important is the ESL when the capacitor is on a board. Unfortunately, this really does depend on the rest of the loop the capacitor sees. The ESL of the same capacitor can change by more than a factor of 20, depending on how it is mounted on a board. It can vary from less than 0.3 nH to more than 8 nH.

Without knowing the rest of the loop- the other hand- the ESL cannot be known. Once the other hand starts to interact, you can easily estimate the ESL of a mounted capacitor, and here’s how.

The inductance of the loop composed of the bottom of the capacitor and the top of the pwr/gnd cavity in the board make up most of the mounted ESL of a capacitor. A good approximation to the loop inductance of this structure is the sheet inductance x the number of squares.

The sheet inductance is 32 pH/mil x h, where h is the depth of the top of the cavity from the top of the board. This can vary from 1 mil in HDI boards to more than 20 mils in cheap four layer boards. If h = 10 mils, the sheet inductance is 320 pH per square of the surface trace and capacitor body.

The number of squares of surface trace is just the length of the surface traces and capacitor body, from via to via, divided by its width. The wider the trace and shorter the length, the fewer the squares.

In a typical 0603 or 0402 capacitor, the body of the capacitor is 2 squares. For via-in-pad mounting, the ESL would be about 2 squares worth of sheet inductance. When h is 1 mils, the ESL would be about 0.032 x 2 = 0.07 nH. When h is 20 mils, the ESL would be about 0.64 nH x 2 = 1.3 nH.

Of course with surface traces from the capacitor pads to the vias that could be 4-10 squares, the mounted ESL of the same capacitor could be as high as 5x these values- ranging from 0.3 nH to 8 nH.

What does it mean for a capacitor vendor to supply an ESL value of 0.4 nH, when the actual mounted ESL depends so much on the rest of the loop the capacitor is part of? It is less than worthless, as it gives the impression you have a real value, when in fact, it is meaningless.

The intrinsic ESL of a capacitor is as meaningful as the sound of one hand clapping.

For more information about signal integrity topics, check out my web site, www.beTheSignal.com

A few years ago, I wrote a column about the then recently released EMC expert system, from IBM, EMSAT. At DesignCon 2009, I learned from Bruce Archambeault, a Distinguished Engineer at IBM and IEEE Fellow, who also happens to be the chief architect of EMSAT, that “every board at IBM goes through EMSAT.”

What could be a better endorsement of a tool than that? Maybe that IBM also requires all their OEM board design vendors to run their IBM specific boards through EMSAT and these vendors have integrated EMSAT into their design flow for all of their boards.

An EMC expert system is like having an EMC expert sitting over your shoulder making sure your board design doesn’t violate any of the more than 16 most important design rules to ensure passing EMC compliance tests.

The “secret sauce”, Bruce says, is not in what the rules are, which are freely shared (see below), but in the details of what constitutes a problem and what you do to fix the errors when you encounter them.

In addition to checking for EMC rule violations, EMSAT now also checks for some signal integrity problems. Below in one place is a handy check list of the various EMC and SI rules  EMSAT checks for in a board layout file. If you want more information about EMSAT, contact Gene Garat at Moss Bay EDA.

With permission from Bruce, here are the EMSAT rules:

EMSAT Rules

EMC

Signal Reference Rules

Critical Net Crossing Split Reference Plane: Critical nets must not cross a split in the adjacent reference plane.

Critical Net Changing Reference Plane:Critical nets must not change reference planes.

Net Near Edge of Reference Plane: Critical nets may not be within a specified distance of the edge of their reference plane.

Wiring and Crosstalk Rules

Critical Net Near I/O net: Critical nets may not be routed within a specified distance from an I/O net.

Length of Exposed Critical Traces: All critical nets must be buried between solid planes. The allowable length of the exposed portion of a critical net may be specified.

Critical Net Isolation (Single-Ended Nets): All critical nets must have empty space or  a “ground-guard” trace on either side of the critical net.

Critical Net Isolation (Differential Nets): All differential critical nets must have a “ground-guard” trace on either side of the differential pair of nets.

Critical Differential Net Length Matching and Spacing: All critical nets must be routed within a specified distance of each other, and the length of the differential pair of nets must match within a specified amount.

Decoupling Rules

Decoupling Capacitor Density: Decoupling capacitors must be placed between all adjacent plane pairs within a specified grid density.

Decoupling Capacitor Distance from IC Power Pin: A decoupling capacitor must be connected between the power and ground-reference planes and be placed within a specified distance from each IC power pin.

IC Power/Ground-Reference Pin Distance to Via: The trace connecting between the IC power and/or ground reference pin to the associated via to the power/ground-reference plane must be no longer than the specified distance.

Decoupling Capacitor Distance to Via: The trace connecting between a decoupling capacitor to the associated via to the power/ground-reference plane must be no longer than the specified distance.

Power/Ground-Reference Trace Decoupling: All power and ground-reference traces longer than a specified length must have a decoupling capacitor within a specified distance from the IC power pin.

Placement Rules

I/O Filter Net Distance: All I/O filters must be placed within a specified distance from the I/O connector.

Distance from Oscillator to Clock Driver: All Oscillators must be placed within a specified distance from the clock driver (or other device) that they drive.

Signal Integrity Rules

Net Integrity

Net Length: Report nets longer than a specified length.

Net Coupling: Signal Nets must not be routed within a specified distance of another signal net and not for longer than another specified distance. Optionally, Layer to Layer coupling can also be checked.

Length of Exposed Critical Traces: All critical nets must be buried between solid planes. The allowable length of the exposed portion of a critical net may be specified.

Net Stub Check: Check for stubs on a net longer than a specified length.

Critical Net Crossing Split Reference Plane: Critical nets must not cross a split in the adjacent reference plane.

Net Near Edge of Reference Plane: Critical nets may not be within a specified distance of the edge of their reference plane.

Via Integrity

Unconnected Via Pads: Unconnected Via Pads are not allowed.

Via Clearance Overlap: Via clearances must not overlap. Either the top and bottom layers, or all layers, can be selected.

Via -> Net Coupling: Signal nets must not be routed within a specified distance of a Via on another signal net. The distance between the Via and the Net must be clear. I.e., no intervening traces.

Via Stub Check: Check for stubs on vias. A via can have 2 violations. One for the stub above the highest connected layer, and one for the stub below the lowest connected layer. Vias that are connected together at the same physical location are combined together for the purposes of stub length calculation.

Decoupling Rules

Decoupling Capacitor Density: Decoupling capacitors must be placed between all adjacent plane pairs within a specified grid density.

Decoupling Capacitor Distance from IC Power Pin: A decoupling capacitor must be connected between the power and ground-reference planes and be placed within a specified distance from each IC power pin.

IC Power/Ground-Reference Pin Distance to Via: The trace connecting between the IC power and/or ground reference pin to the associated via to the power/ground-reference plane must be no longer than the specified distance.

Decoupling Capacitor Distance to Via: The trace connecting between a decoupling capacitor to the associated via to the power/ground-reference plane must be no longer than the specified distance.

Power/Ground-Reference Trace Decoupling: All power and ground-reference traces longer than a specified length must have a decoupling capacitor within a specified distance from the IC power pin.

For more information on this and other signal integrity topics, visit my web site, www.beTheSignal.com

There is an old joke about the guy who dropped a diamond ring on the ground one night. He’s down on his knees looking for it and another fellow comes along and asks to help. They’re both down on their knees for a few minutes with no luck. The stranger then says, “I can’t find it anywhere. Where did you drop it?”

The other guy says, “I dropped it over there,” pointing ten feet away. The stranger replies, “If you dropped it over there, why are you looking over here?” He replies, “Because the lights better over here.”

I think this story illustrates one of the limitations of traditional power integrity analysis. We tend to do what is easy, where the light is, rather than tackle the real questions, because they are hard.

Doing a simple SPICE simulation of the impedance profile of a collection of capacitors is easy, and every engineer should be doing this. But, taking the next step to explore the interaction of the capacitors and the planes, or how the mounting geometry influences the ESL and the resulting impedance profile, is hard. The only tool that will take into account the arbitrary, odd shaped power and ground planes, a fact of life in real world product design, is a 3D field solver.

While many of these tools have jewels of insight hidden within them, they are positioned ten feet away from most engineers, in the darkness. They are hard to understand, hard to use, hard to evaluate if the answer is correct or not, and take a while to spin through a lot of what ifs.

I think the recent announcement by Mentor Graphics at DesignCon 2009, of the release of HyperLynx 8.0, which includes power integrity analysis, now expands the circle of light into the power integrity world. Since its first release more than 15 years ago, HyperLynx has been an incredibly easy to use circuit simulator. With the inclusion of lossy line models and eye diagrams, it enables high speed serial link simulation to greater than 10 Gbps.

This easy to use interface and fast computation speed has been extended to power integrity analysis. Now it is easy to evaluate questions like, does position really matter? What is the impact of a Swiss cheese clearance hole field on the impedance of the decoupling capacitor? What is the impedance profile of the capacitors and the planes? Up to what frequency or rise time are decoupling capacitors really effective? For an odd, irregular shaped power plane, what is the DC resistance and are there any hot spots?

I’ve had the opportunity to take the beta version for a test drive and I think it will dramatically reduce the fear, uncertainty and doubt of designing the power distribution network in your design.