Mark your calendar for our No Myths Allowed Webinar on May 6, 2009, 1 pm EDT.

At DesignCon 2009, I had the opportunity to interview Scott Simpson, Global Development Manager for DuPont about their “embedded capacitor” materials. I put this term in quotes because this is how the class of ultra thin laminates has been described for over 15 years, but it’s wrong and misleading. I’ve been advocating this for a long time.

Ultrathin laminates, dielectric layers for use between the power and ground planes in circuit boards with a thickness of 2 mils or thinner, have a significant performance advantage for the Power Distribution Network (PDN); but, it’s not because of their capacitance, it because of their inductance.

The capacitance of even a 1 mil thin dielectric layer is about 1 nF/sq. in. For a board a few inches on a side, this is only about 10 nF of capacitance. But you might think, “it’s low inductance capacitance,” so it’s really important. However, there is a source of even lower inductance-capacitance, and with orders of magnitude more capacitance, on the die itself.

The on-die decoupling capacitance on most chips is on the order of 100 nF to 1,000 nF. Compared to this, the capacitance in the power and ground planes really doesn’t play a significant role for the PDN. It’s the inductance of thin laminates that is so important, and that is what DuPont recognizes and values.

Their Interra HK04 comes in 25, 18 and 12 microns thick laminates and is currently in production, integrated in a number of high end server products. For the 12 micron layers, its spreading inductance is almost 1/10th that of conventional 4 mil thick laminate power and ground layers, typically, 15 pH per square, compared with the conventional best case values of 130 pH per square.

In high performance boards, the number of capacitors needed for decoupling is determined by their ESL and the target impedance at roughly 100 MHz. Anything that will reduce the ESL of the capacitors will decrease the number of capacitors needed- a direct cost savings.

For example, if each capacitor has been mounted to the board with 300 pH of loop inductance, including the plane’s spreading inductance, using this lower inductance laminate means the possibility of eliminating 1/3 the number of capacitors and still maintaining the same high frequency impedance.

The reason you can eliminate 1/3 the number of capacitors is not because you’ve added all this capacitance in the thin laminate planes, it’s because you’ve reduced some of the ESL of each capacitor, requiring fewer in parallel to achieve the same high frequency impedance.

DuPont is one of the rare “embedded capacitance” suppliers that recognizes this and is not afraid to buck the industry trend and tout the real benefit of reduce inductance, not increased capacitance.

This concept of spreading inductance and the inductance of the planes is a complicated concept and one plagued with misunderstanding and myths in the industry. That’s why we have introduced a new class in 2009 on PDN design, and why DuPont has enlisted the help of Steve Weir, one of my guru’s of signal integrity, to assist their customers in optimizing the design integration of these thin laminates.

The real advantage of ultra thin laminates is low inductance, but somehow “reduced inductance embedded materials” isn’t as catchy as “embedded capacitance materials”, but thanks to DuPont, more designers will hear the real story.