Eric Bogatin's Blog: What I Learned This Month

Next No Myths Allowed Webinar, “Selecting Capacitor Values for the PDN”, Dec 9  2009, 1 pm EDT. Signup now.

The co-evolution of finer pitch packages and higher interconnect density circuit boards has enabled the explosion of mobile products for the consumer market, but is wrecking havoc in the test world.

More than 15 years ago, portable, consumer electronic products such as the hand held camcorder, drove the introduction of fine pitch packages, which have become known as chip scale packages (CSP). With pitches less than 20 mils (0.5 mm) and pad densities much higher than 100/square inch, conventional circuit board technology could not provide the cost effective, high density interconnect for this new generation of mobile product.

Higher density circuit board technology co-evolved along with CSPs. Multi layer build up or high density interconnect (HDI) or micro via substrates all use finer lines and smaller vias than traditional, mechanically drilled circuit boards. Every single cell phone manufactured today uses CSPs and microvia substrates.

While consumer products are well suited to leverage an interconnect form factor of finer pitch CSPs and higher interconnect substrates, the tester environment is not.

From the pin electronics of the tester to the pads on the chip being tested is a complex, Rube Goldberg hierarchy of interconnects. This system is designed to provide high performance electrical connections between thousands of pads on the pin electronics chips to thousands of pads on the die or wafer, and the flexibility of re-using most of the interconnects for thousands of different chip designs and millions of individual parts tested, while still allowing the pin electronics to be field upgradable.

The interface between the tester and the device to be tested is the load board. This is a massive space transformer circuit board. Pads on the bottom surface on 50-100 mil centers touch compliant pins connected to the tester electronics cabling or circuit boards. With more than 10,000 pins, even a 50 gm contact force per pin needs more than 1,000 pounds of force between the load board and the tester. It must be mechanically rigid which is why they are so thick. Typical thickness specs for load boards range from 150 to 200 mils.

To accommodate the more than 10,000 connections to the pin electronics, load boards have to be large, typically more than 15 inches on a side.

The electrical specifications for the load boards have to be higher performance than product boards. It’s not enough that the device works on the load board, the load board must have minimal impact on the signal quality of the device being tested so its intrinsic performance can be evaluated.

This translates to wider traces in controlled impedance with thicker dielectric layers. The long traces will often require more expensive, low loss dielectrics and multiple, solid, power and ground planes. These high performance interconnects are implemented with 16-30 layers of alternating signal layers and power and ground planes.

Load boards are driven by a different set of forces than product boards. They have to be large area, thick, many layers and use high performance, read more expensive, laminate materials.

On the top side of the load board are the connections to the device to be tested. Since the package already provides the space transformer from the die pad pitch to the circuit board pad pitch, historically, just a one to one compliant socket has been needed to interface the package under test to the load board.

As chip scale packages migrate to finer pitch, HDI substrate technology co-evolves to provide the higher interconnect needs. But the load board, with its large area, thick substrate and many layers cannot keep up. Here lies the challenge. How do you fabricate a load board, 200 mils thick, 18 inches on a side with 26 layers and have pads on the surface that can interface to a socket on 0.4 mm centers? And CSPs are migrating to even finer pitch.

While integrating a few HDI layers on top of a conventional load board to do the geometry transformation is being done, it is very expensive in direct cost and in yielded cost.

An alternative solution is to adopt the approach for testing a single die or whole wafer: add a space transformer from the fine pitch pads of the device to the coarse pitch pads of the circuit board.

After all, needle probe cards have been doing this for more than 40 years. Other technologies have evolved for wafer probing that use a ceramic substrate as the space transformer. In the Form Factor probe cards, for example, MEMs compliant tips are fabricated on the top of the ceramic substrate on pitches as fine as 2 mils. The pads on the bottom of the ceramic substrate interface to the load board with another compliant one to one interposer but on pitches of 50 to 100 mils.

This same approach can be implemented for final test of packaged devices. A daughter board acts as the space transformer from the finer pads pitch of the CSP to the coarser pad pitch of the load board.  A fine pitch socket technology is used on the top surface and a board to board interposer is used between the daughter card and the conventional load board.

An example of such an architecture, from R&D Circuits, is shown to the left.

Jim Russell, president of R&D Circuits says the cross over where this approach is lower cost than conventional load boards is for devices with 0.4 mm pitch and below. He goes on to say, “this architecture also allows the same, high value load board, to be used with multiple devices in a related family by just changing out the daughter card.”

In July 2008, R&D Circuit acquired Anestel Corporation which developed a board to board interposer based on patterned Kapton films with columns of silver filled silicone rubber. When compressed between two boards, this film is a one to one interposer. The typical connection pitch is 0.8 mm.

The daughter boards act as the space transformers. Being small size, few layers and high performance, they can ride the HDI wave and evolve with the finer pitch chip scale packages. They shield the load board from technology advances of the package devices, allowing the load board to be optimized for the tester environment.

Our thirst for higher performance, lower cost mobile consumer products will absolutely drive smaller, higher pad density devices, with a form factor indistinguishable from the chip. For load boards to keep up in final test it’s not surprising that the daughter card architecture currently used in wafer sort, should be adopted for package test.

see you in cyberspace!

Next No Myths Allowed Webinar, “Selecting Capacitor Values for the PDN”, Dec 9  2009, 1 pm EDT. Signup now.

“There ain’t no such thing as a free lunch,” is how the phase, popularized in Robert Heinlein’s book, The Moon as a Harsh Mistress, usually goes.

But that’s not how Scott McMorrow, director of engineering at Teraspeed, uses the phrase. He is fond of saying “There ain’t no such thing as a free launch.”

It’s sort of ironic, because he and his team are world experts at providing nearly free launches.

A launch is a transition from one transmission line geometry to another. While a coax cable and a stripline in a circuit board may each be electrically transparent, when one transitions into the other, the interface, or launch, will always show up as a discontinuity.

This discontinuity will cause a reflected signal and a reduction in the transmitted signal, which shows up in the insertion loss. The larger the discontinuity, the bigger the impact on the insertion loss. And, due to the physical size of a launch, it is always more of a problem at higher frequencies.

To minimize the launch discontinuity, Teraspeed recommends using a surface mount SMA connector and carefully optimizing the features of the launch via pad stack.

The figure to the left shows the TDR response of a conventional, well designed launch and a Teraspeed “free launch”, with a roughly 35 psec rise time signal and 5 Ohms per division. This was reported, most recently, at DesignCon 2009 and can be found in the reprinted article on the Simberian web site.

The pad stack includes the capture pads, the via barrel diameter, location of return vias, and clearance holes in any planes. Of course, what works in one board will be not always be the best design in another board due to the precise combination of signal layer and plane layer assignments and dielectric thicknesses.

Translating a specific board’s pad stack into the virtual world of a 3D field solver enables you to quickly optimize the clearance holes for a transparent launch. For example, if the launch impedance is high, make the clearance holes smaller. If the impedance is low, make the clearance holes larger.

This principle of a “free launch” applies to all transitions, especially important from the planar geometry of a circuit board to the 3D geometry of a connector.

Samtec made popular the term, “the final inch” to describe the break out region (BOR) of a circuit board connector’s via field. Using this principle of optimizing a few features in the immediate region of the launch, they can make the circuit board transitions into their connectors nearly transparent.

When done well, the transition from any connector to board traces can be transparent. This is important when designing test vehicles, ATE load boards and high performance product boards. As PCIe and USB enter the 5 Gbps and above regime, designing transparent launches will be an important skill.

For information on this and other multi gigabit topics, check out our new class, Multi Giga Bit Design (MGBD).

Hope to see you in cyber space at our next webinar!

Next No Myths Allowed Webinar, “Selecting Capacitor Values for the PDN”, Dec 9  2009, 1 pm EDT. Signup now.

Our last webinar, “Stack up Design of Differential Pairs”, had over 600 registered viewers. If you missed it, you can still watch the recording for free.  The positive response was overwhelming. Surprisingly, most of the emails I got back were about a comment I made in passing.

“The single-ended impedance of one line does not change as an adjacent, grounded line is brought closer.” This is in contrast to the odd mode impedance of one line which will decrease as an adjacent line is brought closer.

Many people said they did not think the single-ended impedance would really be constant- it should decrease. Colin Warwick and Steve Martin, independently, went to the effort of running a simulation to check this out.

Steve did a super analysis and sent me the plot to the left which shows what is going on. In his example of two coupled microstrips, the line widths were 300 microns, which is 12 mils. The dielectric thickness he used was 254 microns, or 10 mils. This comes out as a relatively high impedance line, about 70 Ohms, single-ended.

He calculated the odd mode impedance, the even mode impedance and the single-ended impedance of one line as the other line was brought closer.

The center trace in the plot, the green line, is the single ended impedance. It is absolutely constant until a spacing of about 300 mils, which is the line width. Closer than this tight a coupling, the single-ended impedance begins to drop. But, as long as the spacing is greater than the line width, what we would call tightly coupled, the single-ended impedance is constant.

It is only when the two lines are much closer together than tightly coupled, does the single-ended impedance drop. Up until this extreme tight coupling, the single-ended impedance of a line really is constant.

Hope to see you in cyber space at our next webinar!

Next No Myths Allowed Webinar, “Selecting Capacitor Values for the PDN”, Dec 9  2009, 1 pm EDT. Sign up now.

The last pop quiz posted on our web site, was a real test of how well you understand differential impedance and odd mode impedance. If you watched our last free webinar, the answer to this pop quiz would have been obvious.

By definition, the odd mode impedance of a line that is part of a differential pair is always ½ x the differential impedance. If the differential impedance is 100 Ohms, the odd mode impedance of either line is 50 Ohms.

In this question, the single-ended impedance is designed as 50 Ohms. How do you have a single-ended impedance and odd mode impedance of 50 Ohms?  It can only be if there is no coupling between the two lines that make up the pair.

As the coupling increases, the single-ended impedance won’t change, but the odd mode impedance will decrease. The only correct answer to this question is, uncoupled.

It is interesting that only 42% of you got it correct! This means 58% got it wrong. This way of specifying differential impedance: a single-ended impedance and a differential impedance, is a common way of specifying line impedance. Now you know, it’s really specifying uncoupled lines, with a spacing about 3x the line width.

To really understand differential impedance, check out the last webinar I did on “Stack up Design for Differential Pairs”. It’s free!.