Published by Eric Bogatin on 26 Oct 2009
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The co-evolution of finer pitch packages and higher interconnect density circuit boards has enabled the explosion of mobile products for the consumer market, but is wrecking havoc in the test world.
More than 15 years ago, portable, consumer electronic products such as the hand held camcorder, drove the introduction of fine pitch packages, which have become known as chip scale packages (CSP). With pitches less than 20 mils (0.5 mm) and pad densities much higher than 100/square inch, conventional circuit board technology could not provide the cost effective, high density interconnect for this new generation of mobile product.
Higher density circuit board technology co-evolved along with CSPs. Multi layer build up or high density interconnect (HDI) or micro via substrates all use finer lines and smaller vias than traditional, mechanically drilled circuit boards. Every single cell phone manufactured today uses CSPs and microvia substrates.
While consumer products are well suited to leverage an interconnect form factor of finer pitch CSPs and higher interconnect substrates, the tester environment is not.
From the pin electronics of the tester to the pads on the chip being tested is a complex, Rube Goldberg hierarchy of interconnects. This system is designed to provide high performance electrical connections between thousands of pads on the pin electronics chips to thousands of pads on the die or wafer, and the flexibility of re-using most of the interconnects for thousands of different chip designs and millions of individual parts tested, while still allowing the pin electronics to be field upgradable.
The interface between the tester and the device to be tested is the load board. This is a massive space transformer circuit board. Pads on the bottom surface on 50-100 mil centers touch compliant pins connected to the tester electronics cabling or circuit boards. With more than 10,000 pins, even a 50 gm contact force per pin needs more than 1,000 pounds of force between the load board and the tester. It must be mechanically rigid which is why they are so thick. Typical thickness specs for load boards range from 150 to 200 mils.
To accommodate the more than 10,000 connections to the pin electronics, load boards have to be large, typically more than 15 inches on a side.
The electrical specifications for the load boards have to be higher performance than product boards. It’s not enough that the device works on the load board, the load board must have minimal impact on the signal quality of the device being tested so its intrinsic performance can be evaluated.
This translates to wider traces in controlled impedance with thicker dielectric layers. The long traces will often require more expensive, low loss dielectrics and multiple, solid, power and ground planes. These high performance interconnects are implemented with 16-30 layers of alternating signal layers and power and ground planes.
Load boards are driven by a different set of forces than product boards. They have to be large area, thick, many layers and use high performance, read more expensive, laminate materials.
On the top side of the load board are the connections to the device to be tested. Since the package already provides the space transformer from the die pad pitch to the circuit board pad pitch, historically, just a one to one compliant socket has been needed to interface the package under test to the load board.
As chip scale packages migrate to finer pitch, HDI substrate technology co-evolves to provide the higher interconnect needs. But the load board, with its large area, thick substrate and many layers cannot keep up. Here lies the challenge. How do you fabricate a load board, 200 mils thick, 18 inches on a side with 26 layers and have pads on the surface that can interface to a socket on 0.4 mm centers? And CSPs are migrating to even finer pitch.
While integrating a few HDI layers on top of a conventional load board to do the geometry transformation is being done, it is very expensive in direct cost and in yielded cost.
An alternative solution is to adopt the approach for testing a single die or whole wafer: add a space transformer from the fine pitch pads of the device to the coarse pitch pads of the circuit board.
After all, needle probe cards have been doing this for more than 40 years. Other technologies have evolved for wafer probing that use a ceramic substrate as the space transformer. In the Form Factor probe cards, for example, MEMs compliant tips are fabricated on the top of the ceramic substrate on pitches as fine as 2 mils. The pads on the bottom of the ceramic substrate interface to the load board with another compliant one to one interposer but on pitches of 50 to 100 mils.
This same approach can be implemented for final test of packaged devices. A daughter board acts as the space transformer from the finer pads pitch of the CSP to the coarser pad pitch of the load board. A fine pitch socket technology is used on the top surface and a board to board interposer is used between the daughter card and the conventional load board.
An example of such an architecture, from R&D Circuits, is shown to the left.
Jim Russell, president of R&D Circuits says the cross over where this approach is lower cost than conventional load boards is for devices with 0.4 mm pitch and below. He goes on to say, “this architecture also allows the same, high value load board, to be used with multiple devices in a related family by just changing out the daughter card.”
In July 2008, R&D Circuit acquired Anestel Corporation which developed a board to board interposer based on patterned Kapton films with columns of silver filled silicone rubber. When compressed between two boards, this film is a one to one interposer. The typical connection pitch is 0.8 mm.
The daughter boards act as the space transformers. Being small size, few layers and high performance, they can ride the HDI wave and evolve with the finer pitch chip scale packages. They shield the load board from technology advances of the package devices, allowing the load board to be optimized for the tester environment.
Our thirst for higher performance, lower cost mobile consumer products will absolutely drive smaller, higher pad density devices, with a form factor indistinguishable from the chip. For load boards to keep up in final test it’s not surprising that the daughter card architecture currently used in wafer sort, should be adopted for package test.
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