Published by Eric Bogatin on 14 Jun 2011
Imagine you are standing between the Vdd and Vss pads of a chip, looking outward into the PDN. What impedance will you see? This is the most important question to answer in designing the PDN and in knowing how robust it will be in all possible applications.
The goal in robust and cost effective PDN design is to keep the impedance, as seen by the pads on the ship, to be below a target impedance across the important frequency range of application, typically from DC to the bandwidth of the clock. And, at the same time, you want to accomplish this at the lowest cost. So, what do you see?
Even if the board where the package is mounted were a dead short, the impedance the chip sees may still not be low. The chip’s pads will see the on-die capacitance and the series inductance of the package leads to the board’s PDN interconnects.
This parallel combination of LR from the package and C from the die creates a parallel resonance peak impedance. This can be simulated in a simple SPICE circuit shown here:
It’s this mountain of impedance, as shown above, that is the challenge to overcome for all semiconductor vendors. It will set the ultimate limit to the impedance profile of the entire PDN ecology.
This mountain of impedance, my buddy, Steve Weir, one of the smartest SI engineers I know, calls the "Bandini Mountain."
In 1984, to advertise their huge production capability for fertilizer, the Bandini Fertilizer Company made a series of commercials with Olympic athletes competing with a 100 foot high "simulated" mountain of manure. There was a pole vault, a shot put and a triple jump, all landing on the "mountain".
Since then, a "Bandini Mountain" has been used to refer to any tall pile of manure. This is an appropriate description of the large parallel peak impedance in the PDN ecology.
This Bandini Mountain of impedance is exactly what is typically measured when you look from the pads of the die. Here is an example of the measured Bandini Mountain in an Intel processor chip published in the Intel Technology Journal, Nov 2005
To manage the Bandini Mountain, there are design features the semiconductor vendor can implement, such as more on-die capacitance, less package lead inductance and more on-package capacitance. The use of higher ESR capacitors will also help damp out the peak. But, they all cost money.
The board designer is pretty limited in what can be done to reduce this Bandini Mountain. Even if the board were a dead short, the mountain will still be there. Indeed, any additional series inductance in the board level PDN will only increase the peak of the mountain. This is why minimizing the inductance of the PDN is such an important design task.
There is really only one thing a board vendor can do to reduce the Bandini mountain peak height, and it’s rather counter intuitive. If the board looks resistive to the chip, the resistance may help to damp out the parallel impedance peak. This is why the selection of capacitor values is so important. If they can be adjusted to provide a flat impedance response, looking resistive, when combined with the L of the package and the C of the on-die, the peak height may be reduced.
If you want to learn more about taming the Bandini Mountains in your designs, you’ll want to check out the new PDN class we’ve put together and will be offering in the Fall of 2011. Check out our web site, www.beTheSignal.com, in the next few weeks and we will be posting the fall and winter SI Training Institute schedule. I hope to see you there!