Published by Eric Bogatin on 29 Oct 2011
Optimized Placement of Decoupling Capacitors to Reduce Effective Inductance, presented at the 2011 IEEE EMC Conference
Does location matter for decoupling capacitors? Of course, the only answer is, “it depends.” And the only way to answer this question is by putting in the numbers.
Bruce Archembeault, Jingook Kim, Sam Connor and Jun Fan address this question in the paper they presented at the 2011 IEEE EMC Conference. Unfortunately, it is only available through the IEEE Xplore service, for which you have to pay to access the full pdf text.
They look at three interesting location questions in regards to capacitor placement:
- relative orientation of two adjacent capacitors
- distance below the surface of the power/gnd plane cavity
- configuration around the package of multiple capacitors.
In one example, they calculate the effective inductance, as seen by a central point in the planes, looking out to two capacitors. One is in a fixed position and the other is moved around the observation point along a circular arc.
The authors say, “If two capacitors are used with the same connection inductance and ESL, then the new effective inductance would be one-half of the individual capacitor’s effective inductance. However, this is not correct, especially if the capacitors are placed near to each other.”
They calculate the impact on the effective parallel inductance of the two capacitors as one capacitor is moved around the circular arc, for a cavity with a 10 mil thickness between the power and ground planes. They calculate the contribution from the mounting inductance and cavity spreading inductance for different radii, from 0.25 inches to 1 inch.
As expected, the closer the capacitors to the observation point, the lower the effective inductance. Reducing the distance from 1 inch to 0.25 inches, reduces the effective inductance from about 475 pH to 340 pH, for this specific configuration.
The lowest effective inductance is when the capacitors are on opposite sides of the package and their currents do not overlap in the cavity. But, they say, most of the drop in effective inductance occurs for a separation of about 90 degrees. This suggests a good design guideline, spread capacitors out around the circumference of a package to gain the most benefit from multiple capacitors.
They explore the importance of this guideline by calculating the effective inductance of a collection of 16 capacitors spread around a package, in various configurations, as shown in the figure at the top of this page.
The graph to the left shows the calculated effective inductance of the 16 capacitors in parallel in these four different configurations.
The effective inductance depends on two components, the interactions in the currents in getting down to the cavity through the vias and in the spreading inductance in the cavity.
The biggest impact in reducing the cavity spreading inductance is to spread the capacitors out. When the cavity is at the surface so most of the inductance is cavity inductance, spreading capacitors around the package reduces the cavity inductance by 30%. The relative orientation of the capacitors’ vias is a second order factor.
Does capacitor location matter? Of course, the thicker the cavity, the more important the spreading inductance, and the more important is location. This analysis supports the commonly referenced design guidelines for capacitor placement; if it’s free:
- spread capacitors around the package
- closer is better
- locate the cavity as close to the surface of the board as possible
- alternate polarity of capacitor vias when in close proximity
And a very important guideline: to make the cavity more transparent, use as thin a dielectric between the power and ground planes as you can afford.