Published by Eric Bogatin on 24 Jan 2012 at 09:49 pm
Ask the Signal Integrity Experts Panel at DesignCon 2012, Wed 2 pm in the ChipHead Theater
I’ve assembled a few of the signal integrity experts I turn to when I have a technical question to join me in an “Ask the Experts” panel at DesignCon 2012.
On Wed Feb 1 at 2:00-2:45 pm in the ChipHead Theater, I will moderate a panel discussion, “Ask the experts, anything goes”. Included on the panel of experts are:
- Scott McMorrow, Teraspeed
- Bruce Archambeault, IBM
- Jim Nadolny, Samtec
- Yuriy Shlepnev, Simberian
- Ravi Kollipara, Rambus
- Jianmin Zhang, Cisco
- Jason Miller, Oracle
I have the best job in the world. I get to solicit questions from the audience and pose them to the panel. As an experiment, I will also accept questions by twitter.
On twitter, send your questions to @beTheSignal and use #SIDoctorIsIn.
If you heard a design guideline that just didn’t sound right, if you just released a design to fab and are staying up at night worrying about an iffy design feature, if you need the correct answer to settle an argument with your design team, come to this once in a lifetime opportunity to ask the world’s top signal integrity experts, personally.
You are guaranteed to learn something new and important from this exciting panel discussion.
- Should decoupling capacitors go on top of the board, or on the bottom of the board?
- Should DC blocking caps go near the TX or the RX?
- Should meander lines have a few long loops or many short loops?
- Which is better, tight or loose coupled differential pairs?
- Does a microstrip transmission line really cause EMC failures?
- What are the three most commons sources of failure in DDR3 designs?
- Where does the return current in a common signal go when it transitions from a circuit board to an unshielded twisted pair cable
Of course, the answer is always, “…it depends”, but learn from the experts, on what it depends.
See you there!
Nick Langstoon on 28 Jan 2012 at 4:21 am #
Dr,
How can you estimate trace widths, for the trace lengths about 5cm) from a 100 ohm diff pair layout that transitions to 50 ohm single ended to the edge of the board to 50 ohm connectors.
As the traces gradually separate from the diff to SE, the return current gradually shifts from coupled trace to the return plane.
Chinh nguyen on 31 Jan 2012 at 8:42 am #
There increasing number of ps rails required for FPGA. The power/ground pair would leave room for signals to be routed across splitted power planes. Is it better to imbedded those highly segmented planes between ground planes? If so, any disadvantages?
Chinh nguyen on 31 Jan 2012 at 8:50 am #
If the regulator and the load are placed on the left side of the pwb, the right side is not used for that power rail. All the decoupling capacitors are on the left side. What are the disadvantanges of extending the planes to the right side? Can this un-used plane radiate? Add decoupling caps, add stitching ground via
Eric Bogatin's Blog: What I Learned This Month » Brand New Feature to the beTheSignal Blog- Frequently Asked Questions (FAQs) on 12 Mar 2012 at 1:00 pm #
[...] the most recent DesignCon 2012, I moderated a panel discussion, “Ask the experts,… anything goes.” We had seven industry experts field questions from an [...]
boris bakshan on 26 Apr 2013 at 1:33 am #
Hi,
Are some of the answers for the questions presented here going to be published on “bethe signal”?