Published by Eric Bogatin on 08 Aug 2012 at 08:02 am
At the IEEE EMC Global EMC and SI University, Rick Hartley, a 47 year veteran of the circuit board design, SI and EMC industry, presented a short, personal account of a few of the more interesting problem boards he’s worked on over the years.
He offered a few gems of insight along the way.
“Its much easier to design a board that works the first time, and much harder to find a problem and fix it. Anything you do to fix a board after the fact is really just a band aid.”
“To control noise and EMI, we need to control containment of the electric and magnetic fields.”
He echoed the theme of the Global University: “Return paths are not just important, they are everything.”
When asked the difference between an SI problem and an EMC problem, he said, “An SI problem is when you step on your own toes. An EMC problem is when you step on someone else’s toes.”
Rick offered four examples of boards with problems, and the fixes which turned a crisis into a success.
Example #1: In a four layer board, low density board, the surface microstrip traces were referenced to a 5v plane, but no low impedance path was provided for the return current to get back to the 0v plane, connected to the driver. He re-routed the adjacent plane to be the 0v plane, and EMI problem went away. Moral of the story: follow the return paths.
Example #2: In a high speed, multi layer board, the I/O section was carefully designed to minimize any common currents which could get out on the many 100 Mbps cables. As all the I/O were differential, the ground plane along the edge of the board was isolated from the board and only differential signals were allowed to cross the gap. But the board still radiated from the cables.
Then he noticed there were dozens of LED control lines that crossed the gap to light up the connectors. Even though they were “low speed”, they had just as fast an edge as the data. After adding low pass filters to the LED control lines, problem was eliminated. Moral of the story: “just because you think a line is low speed, doesn’t mean it is.
Example #3: “The best example of a the worst design.” The control board, with two processors and two memory banks was an 18 layer board. Many of the signal layers were filled with serpentines to keep the length skew between all the control to memory connections within 50 mils, even though the clock was 133 MHz. To keep costs down, the 18 layer board had 4 signal layers between planes- difficult to control impedance and very high cross talk.
When he evaluated the timing, his team agreed that 300 psec was the timing skew they needed, which was a length skew of about +/- 1 inch. With this skew, the board routing could be reduced to only 10 layers, with two signals between planes, a more robust design. Moral of the story: overly tight constraints may increase the complexity of the board and introduce new problems.
Example #4: Taken from Lee Ritchey’s book, showed a 6 layer board, with large spacing between the power and ground planes, failing an EMC test. After copper fill was added to the signal layers, the board passed the radiated emissions test.
They say an expert is someone who has made all the mistakes possible. I always learn something listening to an expert. This is partly why this Global U is so valuable.