Next No Myths Allowed Webinar, “Selecting Capacitor Values for the PDN”, Dec 9  2009, 1 pm EDT. Signup now.

“There ain’t no such thing as a free lunch,” is how the phase, popularized in Robert Heinlein’s book, The Moon as a Harsh Mistress, usually goes.

But that’s not how Scott McMorrow, director of engineering at Teraspeed, uses the phrase. He is fond of saying “There ain’t no such thing as a free launch.”

It’s sort of ironic, because he and his team are world experts at providing nearly free launches.

A launch is a transition from one transmission line geometry to another. While a coax cable and a stripline in a circuit board may each be electrically transparent, when one transitions into the other, the interface, or launch, will always show up as a discontinuity.

This discontinuity will cause a reflected signal and a reduction in the transmitted signal, which shows up in the insertion loss. The larger the discontinuity, the bigger the impact on the insertion loss. And, due to the physical size of a launch, it is always more of a problem at higher frequencies.

To minimize the launch discontinuity, Teraspeed recommends using a surface mount SMA connector and carefully optimizing the features of the launch via pad stack.

The figure to the left shows the TDR response of a conventional, well designed launch and a Teraspeed “free launch”, with a roughly 35 psec rise time signal and 5 Ohms per division. This was reported, most recently, at DesignCon 2009 and can be found in the reprinted article on the Simberian web site.

The pad stack includes the capture pads, the via barrel diameter, location of return vias, and clearance holes in any planes. Of course, what works in one board will be not always be the best design in another board due to the precise combination of signal layer and plane layer assignments and dielectric thicknesses.

Translating a specific board’s pad stack into the virtual world of a 3D field solver enables you to quickly optimize the clearance holes for a transparent launch. For example, if the launch impedance is high, make the clearance holes smaller. If the impedance is low, make the clearance holes larger.

This principle of a “free launch” applies to all transitions, especially important from the planar geometry of a circuit board to the 3D geometry of a connector.

Samtec made popular the term, “the final inch” to describe the break out region (BOR) of a circuit board connector’s via field. Using this principle of optimizing a few features in the immediate region of the launch, they can make the circuit board transitions into their connectors nearly transparent.

When done well, the transition from any connector to board traces can be transparent. This is important when designing test vehicles, ATE load boards and high performance product boards. As PCIe and USB enter the 5 Gbps and above regime, designing transparent launches will be an important skill.

For information on this and other multi gigabit topics, check out our new class, Multi Giga Bit Design (MGBD).

Hope to see you in cyber space at our next webinar!